MPC8540 datasheet(1247/1302 Pages) FREESCALE

1247 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-35

16.4.3.7, 16-88

Add the following two paragraphs at the beginning of the section:

“PCI-X configuration transactions are similar to PCI configuration

transaction as described in Section 16.4.2.11, “Configuration Cycles.” The

exceptions are noted in this section.

There is a rare situation where an internal access (originating from either the

processor core, or other I/O ports on the device) to the 256-byte PCI-X

configuration header may be corrupted by concurrent outbound PCI-X data

transactions. The corruption does not occur if the PCI-X configuration

transactions and the outbound PCI-X data transactions are not concurrent.

The corruption does not occur with inbound PCI-X traffic. This is an issue

for any system that mixes internally generated PCI-X configuration

transactions with outbound PCI-X data transactions. There are two ways to

avoid the situation:

Table 16-62. PCI-X Split Completion Message Summary

Name

Description

31:28

Message Class

A split completion message can be one of the following classes:

0x0 Write completion

0x1 PCI-X bridge error

0x2 Completer error

0x3–0xFReserved

27:20

Message Index

The message index identifies the type of message within the message class.

For write completion message class:

0x00 Normal completion

For PCI-X bridge error message class:

0x00 Master-abort

0x01 Target-abort

0x02 Write data parity error

For completer error message class:

0x00 Byte count out-of-range error

0x01 Split write data parity error

0x8n Device-specific error

—

Reserved

18:12

Remaining

Lower Address

If the split request was a burst memory read transaction, the remaining lower address is

the least significant seven bits of the first byte of data that has not been sent. If the split

request was a DWORD transaction, the completer places all zeroes in this field.1

1 Note that the PCI-X 1.0 specification states that if the split request is a DWORD transaction, the completer sets the

remaining lower address field (bits 18–12) of the split completion message to zero. However, the MPC8540 deviates

from the specification when the split request is a DWORD read transaction to the upper 32 bits of a quad word (that

is, the address ends with 1xx); in this case, bit 14 of the split completion message is set to 1.

11:0

Remaining Byte

Count

If the split request was a burst memory read transaction, the remaining byte count is the

number of bytes that have not been sent. If the split request was a DWORD transaction,

the completer places 0x004 in this field.

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