MPC8540 datasheet(1250/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-38

Freescale Semiconductor

Revision History

17.3.1.5, 17-16

In Table 17-11, correct the PEFCAR[CTLS] bitfield state description to

read as follows:

“0

The RapidIO controller does not support the large common transport

route field.

The RapidIO controller supports the large common transport route

field."

17.3.1.20, 17-30

In Table 17-26, add the following cross-reference to the field description for

PLMREQCSR[C]:

“See Table 17-85 for command symbol formats.”

17.4.1, 17-83

In Table 17-83, add the following to the "Comments" field for

"Maintenance Class" reads:

"Although possible to execute, RapidIO maintenance reads from memory

locations outside of the RapidIO architectural memory space

(0xC_0000–0xC_FFFC) return unreliable data."

17.4.1, 17-86

In Table 17-85, add the following to the "Comments" field of the symbol

type 5 (Link Request) control symbol format description:

"Note that the RapidIO controller causes a checkstop if a software-initiated

send training link request command collides with an inbound send training

link request which is immediately followed by an inbound training pattern."

18.4, 18-4

In Table 18-3, change the reset value of the GPINDR register to be

0xnnnn_0000.

18.4.1.9, 18-11

In Figure 18-9, change the reset value of the GPINDR register to be

nnnn_nnnn_nnnn_nnnn_0000_0000_0000_0000.

18.4.1.14, 18-17

In Table 18-17, change the bit ranges “32–47” to “0–15” and “48–63” to

“16–31”.

18.5.1.5.3, 18-23

Add the following sentence to the end of the first paragraph:

“Note that the DDR controller does not shut down unless

DDR_SDRAM_INTERVAL[REFINT] is set to a non-zero value. See

Section 9.4.1.7, “DDR SDRAM Interval Configuration

(DDR_SDRAM_INTERVAL),” for details.”

19.3.1, 19-4

In Table 19-1, correct the name of the register with offset 0xE_1094 from

PMLCB5 to PMLCB8.

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