MPC8540 datasheet(1254/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-42

Freescale Semiconductor

Revision History

TFC_PAUSE is then set, the MAC stops transmission of data frames after

the current transmission completes. The GTSC interrupt in the IEVENT

transmits a MAC control PAUSE frame with the duration value obtained

from the PTV register. The TXC interrupt occurs after sending the control

pause frame. Next, the MAC clears TFC_PAUSE and resumes transmitting

data frames. Note that if the transmitter is paused due to user assertion of

GTS or reception of a PAUSE frame, the MAC may still transmit a MAC

control PAUSE frame.

No outstanding pause frame transmission request.

Pause frame transmission requested.”

21.5.3.4.2, 21-31

In Table 21-22, replace the description for the RSTAT[QHLT] field with the

following:

“RxBD queue is halted. When IEVENT[BSY] or IEVENT[EBERR] is set

during reception of a packet, RSTAT[QHLT] is also set. In order to begin

receiving packets again, the user must clear RSTAT[QHLT]. This bit is set

whenever the FEC reads an RxBD with its Empty field cleared or

encounters a system bus error while processing an RX packet. It is a

hardware-initiated stop indication (DMA_CTRL[GRS] being set by the

user does not cause this bit to be set.). The current frame and all other frames

directed to the halted queue are discarded. A write with a value of 1

re-enables the queue for receiving.

RxBD queue is enabled for Ethernet reception. (That is, it is not

halted.)

All Ethernet controller receive activity to RxBD queue is halted.”

21.5.3.4.2, 21-30

Replace Figure 21-23 with the following figure:

21.5.3.6.1, 21-37

In Table 21-28, add the following sentence to the MACCFG1[Rx_EN] field

description:

“If set, prior to clearing this bit, set DMACTRL[GRS] then confirm

subsequent occurrence of the graceful receive stop interrupt

(IEVENT[GRSC] is set).”

R 0

000 0000

QHLT

000 0000 0000 0000 00000

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

0x2_6304

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