MPC8540 datasheet(1256/1302 Pages) FREESCALE

1256 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-44

Freescale Semiconductor

Revision History

21.6.2.2, 21-48

Replace the soft reset steps with the following:

1.Set GTS bit in DMACTRL register.

2.Poll GTSC bit in IEVENT register until detected as set.

3.Clear both Rx_EN and Tx_EN bits in MACCFG1.

4.Wait for a period of 9.6 Kbytes worth of data on the interface (~8ms

worst case).

5.Set GRS bit in DMACTRL register.

6.Poll GRSC bit in IEVENT register until detected as set.

7.Set Soft_Reset bit in MACCFG1 register.

8.Clear Soft_Reset bit in MACCFG1 register.

9.Load TBASE with new TxBD pointer.

10.Load RBASE with new RxBD pointer.

11.Set up other MAC registers (MACCFG2, MAXFRM, and so on).

12.Set WWR and WOP bits in DMACTRL register.

13.Clear THLT bit in TSTAT register and QHLT bit in RSTAT register by

writing 1 to these bits.

14.Clear GRS/GTS bits in DMACTRL. (Do not change other bits.)

15.Enable Tx_EN/Rx_EN in MACCFG1 register.

21.6.2.3, 21-49

Replace the second paragraph with the following:

"If the user has a frame ready to transmit, a transmit-on-demand function

may be emulated while in polling mode by using the graceful-transmit-stop

feature. First, clear the IMASK[GTSCEN] bit to mask the

graceful-transmit-stop complete interrupt. Next set, then immediately clear

the DMACTRL[GTS] bit. Clear the resulting IEVENT[GTSC] bit. Finally,

the IMASK[GTSCEN] bit may be set once again."

21.6.2.3, 21-50

Insert the following sentence between the third and (formerly) fourth

sentences of the sixth paragraph:

"The pause duration is defined by the received pause control frame and

begins when the frame was first received."

21.6.2.5.2, 21-54

Replace the third and fourth sentences of the first paragraph with the

following:

“The eight high-order bits of a cyclic redundancy check (CRC) checksum

are used to index into the hash table.”

MPC8540 Datasheet(PDF) 1256 Page - Freescale Semiconductor, Inc