MPC8540 datasheet(1252/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-40

Freescale Semiconductor

Revision History

20.4.6.1, 20-29

In Table 20-27, replace the “Function” description of the CMDBC field

with the following:

“Byte count. Range: 32 to 1 where a value of 0 indicates 32 bytes.

00000 = 32 bytes

00001 = 1 byte

00010 = 2 bytes

...

11110 = 30 bytes

11111 = 31 bytes”

20.4.6.1, 20-30 and 20-31

Change all instances of “TRSEL” and “TRSEL1” to “IFSEL” and all

instances of “TBCR” to “TBCR1”.

21.2, 21-5

In the first bullet item of the FEC features list, change “820.3x” to “802.3x.”

21.5.2, 21-10

In Table

21-3, add the following row:

21.5.2, 21-11

In Table 21-3, change the reset value for the FEC IFSTAT register to be

0x0000_0000.

21.5.3.1.1, 21-14

In Table

21-4, correct the IEVENT[RXC] bitfield description to read as follows:

“Receive control interrupt. A control frame was received. If

MACCFG1[Rx_Flow] is set, a pause operation is performed lasting for the

duration specified in the received pause control frame and beginning when

the frame was received.

Control frame not received

Control frame received”

21.5.3.1.1, 21-14

In Table 21-4, replace the EBERR field description with:

“Ethernet bus error. This bit indicates that a system bus error for a memory

read ocurred while a DMA transaction was underway. If the EBERR is set

while transmission is in progress, the DMA stops sending data to the Tx

FIFO which eventually causes an underrun error (XFUN) and

TSTAT[THLT] is set. If the EBERR is set while receiving a frame, the DMA

discards the frame and RSTAT[QHLT] is set.

No system bus error occurred.

System bus error occurred.”

0x2_604C

FIFO_PAUSE_CTRL—FIFO pause control register

R/W

0x0000_0000

14.5.3.2.1/A-19

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