MPC8540 datasheet(1255/1302 Pages) FREESCALE

1255 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-43

21.5.3.6.1, 21-37

In Table 21-28, add the following sentence to the MACCFG1[Tx_EN] field

description:

“If set, prior to clearing this bit, set DMACTRL[GTS] then confirm

subsequent occurrence of the graceful transmit stop interrupt

(IEVENT[GTSC] is set).”

21.5.3.6.6, 21-41

In Figure 21-34, change the reset value for the FEC IFSTAT register to be

0x0000_0000.

21.5.3.6.6, 21-40 and 21-41

Delete the first sentence and replace Figure 21-35 with the following figure

(exposing the Link Fail status field):

21.5.3.6.6, 21-41

In Table 21-34, replace the last row with the following rows:

21.5.3.7.1, 21-43

Change the second sentence of the first paragraph to read:

“When the DA field of a receive frame is processed through a 32-bit CRC

generator, the 8 high-order bits (0–7) of the CRC remainder are mapped to

one of the 256 entries.”

21.5.3.7.1, 21-43

In Table 21-36, add the following sentence to the IADDRn field description:

“For instance, the MSB of IADDR0 correlates to entry 0 and the LSB of

IADDR7 correlates to entry 255.”

21.5.3.7.2, 21-44

In Table 21-37, add the following sentence to the GADDRn field

description:

“For instance, the MSB of GADDR0 correlates to entry 0 and the LSB of

GADDR7 correlates to entry 255.”

00000000 0000000000000

Excess

Defer

0000

Link

Fail

Reset

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_453C; TSEC2:0x2_553C

23–27

—

Reserved

Link Fail

Link Fail. This bit indicates the status of signal detection.

0 The100X module has detected a “signal detect” for longer than 330 mS.

1 The100X module has detected a “signal detect” for less than 330 mS or not at all.

29–31

—

Reserved

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