MPC8540 datasheet(1258/1302 Pages) FREESCALE

1258 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-46

Freescale Semiconductor

Revision History

•Bit-reversed least-significant byte of CRC value: BR_CRC = 0xAD =

0b10101101

•High-order 3 bits of BR_CRC: HO_CRC = 0b101 = 5

•Low-order 5 bits of BR_CRC: LO_CRC = 0b01101 = 13

•GADDR5 = 0x0004_0000

21.6.2.7, 21-56

In Table 21-44, corrected the RXC description to read as follows:

“Receive control: A control frame was received. As soon as the transmitter

finishes sending the current frame, a pause operation is performed lasting

for the duration specified in the received pause control frame and beginning

when the frame was first received.”

21.6.3.2, 21-63

In Table 21-48, change the LG bitfield description to read:

“Rx frame length violation. Written by TSEC. (Only valid if L is set.) A

frame length greater than maximum frame length was recognized while

MACCFG2[HUGE FRAME] was set. Note, if MACCFG2[HUGE

FRAME] is cleared, the frame is truncated to the value programmed in the

maximum frame length register.”

21.6.4, 21-64

Replace the first paragraph with the following:

“Some applications require the ability to identify selected portions of data

within a frame’s data payload. This process is called extraction although the

data is not truly removed. Rather than literarily extracting a section of the

data and copying it into a new memory location, the data is placed in the L2

cache. This allows the processor to quickly access critical frame

information as soon as the processor is ready without having to first fetch

the data from main memory. This results in substantial improvement in

throughput and hence reduction in latency.”

21.7.1.1, 21-66

In Table 21-50, remove the sixth initialization step.

21.7.1.1, 21-66

n Table 21-50, add the following step immediately following the optional

DMACTRL initialization step:

Initialize FIFO_PAUSE_CTRL,

FIFO_PAUSE_CTRL[0000_0000_0000_0000_0000_0000_0000_0010]

MPC8540 Datasheet(PDF) 1258 Page - Freescale Semiconductor, Inc