MPC8540 datasheet(1262/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Glossary-4

Freescale Semiconductor

General-purpose register (GPR). Any of the 32 registers in the general-purpose

results for all integer data manipulation instructions. Integer load

instructions move data from memory to GPRs and store instructions move

data from GPRs to memory.

Guarded. The guarded attribute pertains to out-of-order execution. When a page is

designated as guarded, instructions and data cannot be accessed

out-of-order.

Harvard architecture. An architectural model featuring separate caches and other

memory management resources for instructions and data.

IEEE 754. A standard written by the Institute of Electrical and Electronics

Engineers that defines operations and representations of binary

floating-point numbers.

Illegal instructions. A class of instructions that are not implemented for a

particular PowerPC processor. These include instructions not defined by the

PowerPC architecture. In addition, for 32-bit implementations, instructions

that are defined only for 64-bit implementations are considered to be illegal

instructions. For 64-bit implementations instructions that are defined only

for 32-bit implementations are considered to be illegal instructions.

Implementation. A particular processor that conforms to the PowerPC

architecture, but may differ from other architecture-compliant

implementations for example in design, feature set, and implementation of

optional features. The PowerPC architecture has many different

implementations.

Imprecise exception. A type of synchronous exception that is allowed not to adhere

to the precise exception model (see Precise exceptions). The PowerPC

architecture allows only floating-point exceptions to be handled

imprecisely.

Inbound ATMU windows. Mappings that perform address translation from the

external address space to the local address space, attach attributes and

transaction types to the transaction, and map the transaction to its target

interface.

Inter-packet gap. The gap between the end of one Ethernet packet and the

beginning of the next transmitted packet.

MPC8540 Datasheet(PDF) 1262 Page - Freescale Semiconductor, Inc