MPC8540 datasheet(1266/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Glossary-8

Freescale Semiconductor

Physical medium attachment (PMA) sublayer. Sublayer responsible for

serializing code groups into a bit stream suitable for serial bit-oriented

physical devices (SERDES) and vice versa. Synchronization is also

performed for proper data decoding in this sublayer. The PMA sits between

the PCS and the PMD sublayers.

Physical medium dependent (PMD) sublayer. Sublayer responsible for signal

transmission. The typical PMD functionality includes amplifier,

modulation, and wave shaping. Different PMD devices may support

different media.

Physical memory. The actual memory that can be accessed through the system’s

memory bus.

Pipelining. A technique that breaks operations, such as instruction processing or

bus transactions, into smaller distinct stages or tenures (respectively) so that

a subsequent operation can begin before the previous one has completed.

Precise exceptions. A category of exception for which the pipeline can be stopped

so instructions that preceded the faulting instruction can complete and

subsequent instructions can be flushed and redispatched after exception

handling has completed. See Imprecise exceptions.

Primary opcode. The most-significant 6 bits (bits 0–5) of the instruction encoding

that identifies the type of instruction.

Program order. The order of instructions in an executing program. More

specifically, this term is used to refer to the original order in which program

instructions are fetched into the instruction queue from the cache.

Protection boundary. A boundary between protection domains.

Protection domain. A protection domain is a segment, a virtual page, a BAT area,

or a range of unmapped effective addresses. It is defined only when the

appropriate relocate bit in the MSR (IR or DR) is 1.

Quad word. A group of 16 contiguous locations starting at an address divisible by

16.

Quiesce. To come to rest. The processor is said to quiesce when an exception is

taken or a sync instruction is executed. The instruction stream is stopped at

the decode stage and executing instructions are allowed to complete to

create a controlled context for instructions that may be affected by

out-of-order, parallel execution. See Context synchronization.

MPC8540 Datasheet(PDF) 1266 Page - Freescale Semiconductor, Inc