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MPC8540 Datasheet(PDF) 1263 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1263 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
Glossary-5
Integer unit. An execution unit in the core responsible for executing integer
instructions.
In-order. An aspect of an operation that adheres to a sequential model. An
operation is said to be performed in-order if, at the time that it is performed,
it is known to be required by the sequential execution model.
Instruction latency. The total number of clock cycles necessary to execute an
instruction and make ready the results of that instruction.
K
Kill. An operation that causes a cache block to be invalidated without writing any
modified data to memory.
L
Latency. The number of clock cycles necessary to execute an instruction and make
ready the results of that execution for a subsequent instruction.
L2 cache. Level-2 cache. See Secondary cache.
Least-significant bit (lsb). The bit of least value in an address, register, field, data
element, or instruction encoding.
Least-significant byte (LSB). The byte of least value in an address, register, data
element, or instruction encoding.
Little endian. A byte-ordering method in memory where the address n of a word
corresponds to the least-significant byte. In an addressed memory word, the
bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most-significant
byte. See Big endian.
Local access window. Mapping used to translate a region of memory to a particular
target interface, such as the DDR SDRAM controller or the PCI controller.
The local memory map is defined by a set of eight local access windows.
The size of each window can be configured from 4 Kbytes to 2 Gbytes.
M
Media access control (MAC) sublayer. Sublayer that provides a logical connection
between the MAC and its peer station. Its primary responsibility is to
initialize, control, and manage the connection with the peer station.
Medium-dependent interface (MDI) sublayer—Sublayer that defines different
connector types for different physical media and PMD devices.



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