MPC8540 datasheet(1267/1302 Pages) FREESCALE

1267 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Glossary-9

rA. The rA instruction field is used to specify a GPR to be used as a source or

destination.

rB. The rB instruction field is used to specify a GPR to be used as a source.

rD. The rD instruction field is used to specify a GPR to be used as a destination.

rS. The rS instruction field is used to specify a GPR to be used as a source.

RapidIO. High-performance, packet-switched, interconnect architecture that

provides reliability, increased bandwidth, and faster bus speeds in an

intra-system interconnect. Designed to be compatible with integrated

communications processors, host processors, and networking digital signal

processors,

Record bit. Bit 31 (or the Rc bit) in the instruction encoding. When it is set, updates

the condition register (CR) to reflect the result of the operation.

Reconciliation sublayer. Sublayer that maps the terminology and commands used

in the MAC layer into electrical formats appropriate for the physical layer

entities.

Referenced bit. One of two page history bits found in each page table entry. The

processor sets the referenced bit whenever the page is accessed for a read or

write. See also Page access history bits.

Requester. In PCI-X, a requester is an initiator that first introduces a transaction into

the PCI-X domain. If a transaction is terminated with a split response, the

requester becomes the target of the subsequent split completion.

Reservation. The processor establishes a reservation on a cache block of memory

space when it executes an lwarx instruction to read a memory semaphore

into a GPR.

Reservation station. A buffer between the dispatch and execute stages that allows

instructions to be dispatched even though the results of instructions on

which the dispatched instruction may depend are not available.

RISC (reduced instruction set computing). An architecture characterized by

fixed-length instructions with nonoverlapping functionality and by a

separate set of load and store instructions that perform memory accesses.

MPC8540 Datasheet(PDF) 1267 Page - Freescale Semiconductor, Inc