MPC8540 datasheet(1264/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Glossary-6

Freescale Semiconductor

Media-independent interface (MII) sublayer. Sublayer that provides a standard

interface between the MAC layer and the physical layer for 10/100-Mbps

operations. It isolates the MAC layer and the physical layer, enabling the

MAC layer to be used with various implementations of the physical layer.

MEI (modified/exclusive/invalid). Cache coherency protocol used to manage

caches on different devices that share a memory system. Note that the

PowerPC architecture does not specify the implementation of a MEI

protocol to ensure cache coherency.

Memory access ordering. The specific order in which the processor performs load

and store memory accesses and the order in which those accesses complete.

Memory-mapped accesses. Accesses whose addresses use the page or block

address translation mechanisms provided by the MMU and that occur

externally with the bus protocol defined for memory.

Memory coherency. An aspect of caching in which it is ensured that an accurate

view of memory is provided to all devices that share system memory.

Memory consistency. Refers to agreement of levels of memory with respect to a

single processor and system memory (for example, on-chip cache,

secondary cache, and system memory).

Memory management unit (MMU). The functional unit that is capable of

translating an effective (logical) address to a physical address, providing

protection mechanisms, and defining caching methods.

Modified state. MEI state (M) in which one, and only one, caching device has the

valid data for that address. The data at this address in external memory is

not valid.

Most-significant bit (msb). The highest-order bit in an address, registers, data

element, or instruction encoding.

Most-significant byte (MSB). The highest-order byte in an address, registers, data

element, or instruction encoding.

NaN.

An abbreviation for not a number; a symbolic entity encoded in

floating-point format. There are two types of NaNs—signaling NaNs and

quiet NaNs.

No-op. No-operation. A single-cycle operation that does not affect registers or

generate bus activity.

MPC8540 Datasheet(PDF) 1264 Page - Freescale Semiconductor, Inc