MPC8540 datasheet(1261/1302 Pages) FREESCALE

1261 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Glossary-3

Completer. In PCI-X, a completer is the device addressed by a transaction (other

than a split completion transaction). If a target terminates a transaction with

a split response, the completer becomes the initiator of the subsequent split

completion.

Context synchronization. An operation that ensures that all instructions in

execution complete past the point where they can produce an exception, that

all instructions in execution complete in the context in which they began

execution, and that all subsequent instructions are fetched and executed in

the new context. Context synchronization may result from executing

specific instructions (such as isync or rfi) or when certain events occur

(such as an exception).

Copy-back operation. A cache operation in which a cache line is copied back to

memory to enforce cache coherency. Copy-back operations consist of snoop

push-out operations and cache cast-out operations.

Direct-mapped cache. A cache in which each main memory address can appear in

only one location within the cache; operates more quickly when the

memory request is a cache hit.

Double data rate. Memory that allows data transfers at the start and end of a clock

cycle. thereby doubling the data rate.

Effective address (EA). The 32-bit address specified for a load, store, or an

instruction fetch. This address is then submitted to the MMU for translation

to either a physical memory or an I/O address.

Exclusive state. MEI state (E) in which only one caching device contains data that

is also in system memory.

Frame-check sequence (FCS). Specifies the standard 32-bit cyclic redundancy

check (CRC) obtained using the standard CCITT-CRC polynomial on all

fields except the preamble, SFD, and CRC.

Fetch. Retrieving instructions from either the cache or main memory and placing

them into the instruction queue.

Flush. An operation that causes a cache block to be invalidated and the data, if

modified, to be written to memory.

MPC8540 Datasheet(PDF) 1261 Page - Freescale Semiconductor, Inc