MPC8540 datasheet(1265/1302 Pages) FREESCALE

1265 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Glossary-7

OCeaN (On-chip network). Non-blocking crossbar switch fabric. Enables full

duplex port connections at 128Gb/s concurrent throughput and independent

per port transaction queuing and flow control. Permits high bandwidth, high

performance, as well as the execution of multiple data transactions.

Outbound ATMU windows. Mappings that perform address translations from local

32-bit address space to the address spaces of RapidIO or PCI/PCI-X, which

may be much larger than the local space. Outbound ATMU windows also

map attributes such as transaction type or priority level.

Packet. A unit of binary data that can be routed through a network. Sometimes

packet is used to refer to the frame plus the preamble and start frame

delimiter (SFD).

Page. A region in memory. The OEA defines a page as a 4-Kbyte area of memory

aligned on a 4-Kbyte boundary.

Page access history bits. The changed and referenced bits in the PTE keep track of

the access history within the page. The referenced bit is set by the MMU

whenever the page is accessed for a read or write operation. The changed

bit is set when the page is stored into. See Changed bit and Referenced bit.

Page fault. A page fault is a condition that occurs when the processor attempts to

access a memory location that does not reside within a page not currently

resident in physical memory. On PowerPC processors, a page fault

exception condition occurs when a matching, valid page table entry

(PTE[V] = 1) cannot be located.

Page table. A table in memory is comprised of page table entries, or PTEs. It is

further organized into eight PTEs per PTEG (page table entry group). The

number of PTEGs in the page table depends on the size of the page table (as

specified in the SDR1 register).

Page table entry (PTE). Data structures containing information used to translate

effective address to physical address on a 4-Kbyte page basis. A PTE

consists of 8 bytes of information in a 32-bit processor and 16 bytes of

information in a 64-bit processor.

Physical coding sublayer (PCS). Sublayer responsible for encoding and decoding

data stream to and from the MAC sublayer. Medium (1000BASEX) 8B/10B

coding is used for fiber. Medium (1000BASET) 8B1Q coding is used for

unshielded twisted pair (UTP).

MPC8540 Datasheet(PDF) 1265 Page - Freescale Semiconductor, Inc