MPC8540 datasheet(1268/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Glossary-10

Freescale Semiconductor

Secondary cache. A cache memory that is typically larger and has a longer access

time than the primary cache. A secondary cache may be shared by multiple

devices. Also referred to as L2, or level-2, cache.

Sequence. In PCI-X, a sequence is one or more transactions associated with

carrying out a single logical transfer by a requester. Each transaction in the

same sequence carries the same unique sequence ID.

Set (v). To write a nonzero value to a bit or bit field; the opposite of clear. The term

‘set’ may also be used to generally describe the updating of a bit or bit field.

Set (n). A subdivision of a cache. Cacheable data can be stored in a given location

in one of the sets, typically corresponding to its lower-order address bits.

Because several memory locations can map to the same location, cached

data is typically placed in the set whose cache block corresponding to that

address was used least recently. See Set associative.

Set associative. Aspect of cache organization in which the cache space is divided

into sections, called sets. The cache controller associates a particular main

memory address with the contents of a particular set, or region, within the

cache.

Slave. The device addressed by a master device. The slave is identified in the

address tenure and is responsible for supplying or latching the requested

data for the master during the data tenure.

Snooping. Monitoring addresses driven by a bus master to detect the need for

coherency actions.

Snoop push. Response to a snooped transaction that hits a modified cache block.

The cache block is written to memory and made available to the snooping

device.

Stall. An occurrence when an instruction cannot proceed to the next stage.

Sticky bit. A bit that when set must be cleared explicitly.

Superscalar machine. A machine that can issue multiple instructions concurrently

from a conventional linear instruction stream.

Supervisor mode. The privileged operation state of a processor. In supervisor

mode, software, typically the operating system, can access all control

registers and can access the supervisor memory space, among other

privileged operations.

MPC8540 Datasheet(PDF) 1268 Page - Freescale Semiconductor, Inc