MPC8540 datasheet(1272/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 1-2

Freescale Semiconductor

E–I

DDR_SDRAM_MODE (DDR SDRAM mode configuration

DDRDLLCR (DDR DLL control register), 18-19

DEVDISR (device disable control register), 18-13

DGSR (DMA general status register), 15-26

DICAR (RapidIO device information capability register),

17-14

DIDCAR (RapidIO device identity capability register), 17-13

DMACTRL (FEC DMA control register), 21-20

DMACTRL (TSEC DMA control register), 14-28

DMR (RapidIO doorbell mode register), 17-77

DOCAR (RapidIO destination operations capability register),

17-19

DQDPAR (RapidIO doorbell queue dequeue pointer address

DQEPAR (RapidIO doorbell queue enqueue pointer address

DSR (RapidIO doorbell status register), 17-78

DSRn (DMA 0–3 destination stride registers), 15-26

ECC_ERR_INJECT (DDR memory data path error injection

mask ECC register), 9-18

ECNTRL (TSEC Ethernet control register), 14-25

EDIS (FEC error disabled register), 21-18

EDIS (TSEC error disabled register), 14-24

EEADR (ECM error address capture register), 8-8

EEATR (ECM error attributes capture register), 8-7

EEBACR (ECM CCB address configuration register), 8-3

EEBPCR (ECM CCB port configuration register), 8-4

EEDR (ECM error detect register), 8-5

EEER (ECM error enable register), 8-6

EIDRn (PIC external interrupt destination registers 0–11),

10-33

EIVPRn (PIC external interrupt vector/priority registers

0–11), 10-32

EOI0 (PIC per-CPU processor end of interrupt register)

also mapped as global EOI, 10-42

ERR_ADDR (PCI/X error address capture register), 16-33

ERR_ATTRIB (PCI/X error attributes register), 16-32

ERR_CAP_DR (PCI/X error capture disable register), 16-30

ERR_DETECT (DDR memory error detect register), 9-21

ERR_DH (PCI/X error data high capture register), 16-34

ERR_DISABLE (DDR memory error disable register), 9-21

ERR_DL (PCI/X error data low capture register), 16-34

ERR_DR (PCI/X error detect register), 16-29

ERR_EN (PCI/X error enable register), 16-31

ERR_EXT_ADDR (PCI/X error extended address capture

ERR_INT_EN (DDR memory error interrupt enable

ERR_SBE (DDR single-bit ECC memory error management

EXST (TSEC extended status register), 14-100

FIFO_TX_STARVE (FEC FIFO transmit starve register),

21-24

FIFO_TX_STARVE (TSEC FIFO transmit starve register),

14-32

FIFO_TX_STARVE_SHUTOFF (FEC FIFO transmit starve

shutoff register), 21-24

FIFO_TX_STARVE_SHUTOFF (TSEC FIFO transmit

starve shutoff register), 14-32

FIFO_TX_THR (FEC FIFO transmit threshold register),

21-23

FIFO_TX_THR (TSEC FIFO transmit threshold register),

14-31

FRR (PIC feature reporting register), 10-16

GADDRn (FEC group address registers 0–7), 21-46

GADDRn (TSEC group address registers 0–7), 14-88

GAS_TIMR (PCI/X gasket timer register), 16-35

GCR (PIC global configuration register), 10-17

GPINDR (general-purpose input data register), 18-12

GPIOCR (GPIO control register), 18-10

GPOUTDR (general-purpose output data register), 18-11

GPPORCR (general-purpose POR configuration register),

18-9

GTBCRn (PIC global timer 0–3 base count registers), 10-21

GTCCRn (PIC global timer 0–3 current count registers),

10-21

GTDRn (PIC global timer 0–3 destination registers), 10-23

GTVPRn (PIC global timer 0–3 vector/priority registers),

10-22

HAFDUP (FEC half-duplex register), 21-41

HAFDUP (TSEC half-duplex register), 14-53

HBDIDLCSR (RapidIO host base device ID lock command

and status register), 17-26

I2CADR (I2C address register), 11-5

I2CCR (I2C control register), 11-6

I2CDFSRR (I2C digital filter sampling rate register), 11-10

I2CDR (I2C data register), 11-9

I2CFDR (I2C frequency divider register), 11-5

I2CSR (I2C status register), 11-7

MPC8540 Datasheet(PDF) 1272 Page - Freescale Semiconductor, Inc

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