MPC8540 datasheet(1276/1302 Pages) FREESCALE

1276 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 1-6

Freescale Semiconductor

S–T

ROWTARn (RapidIO outbound window translation address

registers 0–8) for maintenance transactions, 17-38

ROWTARn (RapidIO outbound window translation address

registers 0–8) for standard transactions, 17-37

RPKT (TSEC receive packet counter register), 14-65

RSTAT (FEC receive status register), 21-32

RSTAT (TSEC receive status register), 14-41

RUND (TSEC receive undersize packet counter register),

14-70

RXCF (TSEC receive control frame packet counter register),

14-67

RXIC (TSEC receive interrupt coalescing configuration

RXPF (TSEC receive pause frame packet counter register),

14-67

RXUO (TSEC receive unknown opcode packet counter

SARn (DMA 0–3 source address registers), 15-18

SARn (DMA 0–3 source address registers for RapidIO

maintenance reads), 15-19

SATRn (DMA 0–3 source attributes registers), 15-16

SOCAR (RapidIO source operations capability register),

17-17

SPICAR (RapidIO switch port information capability

SR (TSEC status register), 14-93

SRn (DMA 0–3 status registers), 15-13

SSRn (DMA 0–3 source stride registers), 15-25

SVR (PIC spurious vector register), 10-19

SVR (system version register), 18-18

TBACR (trace buffer access control register), 20-22

TBADHR (trace buffer access data high register), 20-22

TBADR (trace buffer access data register), 20-23

TBAMR (trace buffer address mask register), 20-19

TBAR (trace buffer address register), 20-19

TBASE (FEC transmit descriptor base address register),

21-28

TBASE (TSEC transmit descriptor base address register),

14-37

TBCA (TSEC transmit broadcast packet counter register),

14-74

TBCRn (trace buffer control registers 0–1), 20-16

TBDLEN (FEC TxBD data length register), 21-27

TBDLEN (TSEC TxBD data length register), 14-35

TBICON (TSEC TBI control register), 14-102

TBIPA (TSEC TBI physical address register), 14-29

TBPTR (FEC transmit buffer descriptor pointer register),

21-28

TBPTR (TSEC transmit buffer descriptor pointer register),

14-37

TBSR (trace buffer status register), 20-21

TBTMR (trace buffer transaction mask register), 20-20

TBYT (TSEC transmit byte counter register), 14-73

TCR (PIC timer control register), 10-24

TCTRL (FEC transmit control register), 21-25

TCTRL (TSEC transmit control register), 14-33

TDFR (TSEC transmit deferral packet counter register),

14-75

TDRP (TSEC drop frame counter register), 14-79

TEDF (TSEC transmit excessive deferral packet counter

TFCS (TSEC transmit FCS error counter register), 14-80

TFRG (TSEC transmit fragment counter register), 14-82

TFRR (PIC timer frequency reporting register), 10-20

TIMING_CFG_1 (DDR SDRAM timing configuration

TIMING_CFG_2 (DDR SDRAM timing configuration

TJBR (TSEC jabber frame counter register), 14-79

TMCA (TSEC transmit multicast packet counter register),

14-74

TNCL (TSEC transmit total collision counter register), 14-78

TOSR (trigger output source register), 20-25

TOVR (TSEC transmit oversize frame counter register),

14-81

TPKT (TSEC transmit packet counter register), 14-73

TR127 (TSEC transmit and receive 65- to 127-byte frame

counter register), 14-61

TR1K (TSEC transmit and receive 512- to 1023-byte frame

counter register), 14-63

TR255 (TSEC transmit and receive 128- to 255-byte frame

counter register), 14-62

TR511 (TSEC transmit and receive 256- to 511-byte frame

counter register), 14-62

TR64 (TSEC transmit and receive 64-byte frame counter

TRMAX (TSEC transmit and receive 1024- to 1518-byte

frame counter register), 14-63

TRMGV (TSEC transmit and receive 1519- to 1522-byte

VLAN frame counter register), 14-64

TSCL (TSEC transmit single collision packet counter

TSTAT (FEC transmit status register), 21-26

TSTAT (TSEC transmit status register), 14-34

TUND (TSEC transmit undersize frame counter register),

14-81

TXCF (TSEC transmit control frame counter register), 14-80

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