MPC8540 datasheet(1274/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 1-4

Freescale Semiconductor

N–P

MINFLR (FEC minimum frame length register), 21-18

MINFLR (TSEC minimum frame length register), 14-26

MIVPRn (PIC messaging interrupt vector/priority registers

0–3), 10-36

MRBLR (FEC maximum receive buffer length register),

21-34

MRBLR (TSEC maximum receive buffer length register),

14-44

MRn (DMA 0–3 mode registers), 15-10

MRTPR (LBC memory refresh timer prescaler register),

13-21

MSGRn (PIC message registers 0–3), 10-30

MSR (PIC message status register), 10-31

MSR (RapidIO mailbox command and status register), 17-22

MxMR (LBC UPM A–C mode registers), 13-19-13-21

NLNDARn (DMA 0–3 next link descriptor address

registers), 15-23

NLSDARn (DMA 0-3 next list descriptor address register),

15-25

ODATR (RapidIO outbound destination attributes register),

17-70

ODCR (RapidIO outbound double-word count register),

17-71

ODPR (RapidIO outbound destination port register), 17-70

ODQDPAR (RapidIO outbound descriptor queue dequeue

pointer address register), 17-68

ODQEPAR (RapidIO outbound descriptor queue enqueue

pointer address register), 17-72

OMR (RapidIO outbound mode register), 17-65

ORn (LBC options registers 0–7), 13-12-13-18

OSAR (RapidIO outbound source address register), 17-69

OSR (RapidIO outbound status register), 17-67

OSTBD (FEC out-of-sequence TxBD register), 21-29

OSTBD (TSEC out-of-sequence TxBD register), 14-38

OSTBDP (FEC out-of-sequence Tx data buffer pointer

OSTBDP (TSEC out-of-sequence Tx data buffer pointer

PCCSR (RapidIO port control command and status register),

17-33

PCI configuration header registers, 16-36-16-53

see also General Index

PCIDR (programmed context ID register), 20-24

PCIX_TIMR (PCI-X split completion timer register), 16-36

PCR (RapidIO port configuration register), 17-35

PECR (RapidIO port error control register), 17-52

PECRx (RapidIO packet error registers)

see PEPR1x and PEPR2x

PEFCAR (RapidIO processing element features capability

PEIR (RapidIO port error injection register), 17-35

PELLCCSR (RapidIO processing element logical layer

control command and status register), 17-24

PEPCSR0 (RapidIO port error packet/control symbol register

0), 17-52

PEPR1 (RapidIO port error packet register 1), 17-53

PECR1T1 (packet error capture register 1, type 1), 17-53

PECR1T10 (packet error capture register 1, type 10), 17-56

PECR1T11 (packet error capture register 1, type 11), 17-57

PECR1T13 (packet error capture register 1, type 13), 17-58

PECR1T2 (packet error capture register 1, type 2), 17-54

PECR1T5 (packet error capture register 1, type 5), 17-54

PECR1T6 (packet error capture register 1, type 6), 17-55

PECR1T8R (packet error capture register 1, type 8

response), 17-56

PECR1T8RQ (packet error capture register 1, type 8

request), 17-55

PEPR2 (RapidIO port error packet register 2), 17-58

PECR2T10 (packet error capture register 2, type 10), 17-60

PECR2T11 (packet error capture register 2, types 11 and

13), 17-61

PECR2T125 (packet error capture register 2, types 1, 2,

and 5), 17-58

PECR2T6 (packet error capture register 2, type 6), 17-59

PECR2T8R (packet error capture register 2, type 8

response), 17-60

PERTR (RapidIO port error recovery threshold register),

17-64

PESCSR (RapidIO port error and status command and status

PGCCSR (RapidIO port general control command and status

PIR (PIC processor initialization register), 10-18

PITARn (PCI/X inbound translation address registers 1–3),

16-25

PIWARn (PCI/X inbound window attributes registers 1–3),

16-26

PIWBARn (PCI/X inbound window base address registers

1–3), 16-25

PIWBEARn (PCI/X inbound window base extended address

registers 1–3), 16-26

PLASCSR (RapidIO port local ackID status command and

status register), 17-31

PLMREQCSR (RapidIO port link maintenance request

command and status register), 17-29

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