MPC8540 datasheet(1277/1302 Pages) FREESCALE

1277 / 1302 page

U–W

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 1-7

TXCL (TSEC excessive collision packet counter register),

14-78

TXIC (TSEC transmit interrupt coalescing configuration

TXPF (TSEC transmit pause control frame counter register),

14-75

UAFRn (DUART alternate function registers 0–1), 12-17

UDLBn (DUART divisor least significant byte registers 0–1),

12-7

UDMBn (DUART divisor most significant byte registers

0–1), 12-7

UDSRn (DUART DMA status registers 0–1), 12-6, 12-18

UFCRn (DUART FIFO control registers 0–1), 12-11

UIER (DUART interrupt enable register), 12-9

UIIRn (DUART interrupt ID registers 0–1), 12-10

ULCRn (DUART line control registers 0–1), 12-12

ULSRn (DUART line status registers 0–1), 12-15

UMCRn (DUART MODEM control registers 0–1), 12-14

UMSRn (DUART MODEM status registers 0–1), 12-16

URBRn (DUART receiver buffer registers 0–1), 12-3, 12-6

USCRn (DUART scratch registers 0–1), 12-17

UTHRn (DUART transmitter holding registers 0–1), 12-3,

12-6

VIR (PIC vendor ID register), 10-17

WHOAMI0 (PIC per-CPU who am I register—P0)

also mapped as global WHOAMI, 10-41

WMAMR (watchpoint monitor address mask register), 20-14

WMAR (watchpoint monitor address register), 20-13

WMCRn (watchpoint monitor control registers 0–1), 20-11

WMSR (watchpoint monitor status register), 20-16

WMTMR (watchpoint monitor transaction mask register),

20-14

MPC8540 Datasheet(PDF) 1277 Page - Freescale Semiconductor, Inc