MPC8540 datasheet(1281/1302 Pages) FREESCALE

1281 / 1302 page

D–D

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 2-3

configuration, example, 9-28

data beat ordering, 9-45

debug mode

signal selection (POR), 4-20, 4-21

source and target ID, 20-4, 20-26

DLL control (global utilities), 18-19

error checking and correcting (ECC), 9-46

testing ECC with error injection, 9-17-9-19

error handling, 9-19, 9-48

features, 9-2

functional description, 9-25

initialization/application information, 9-49

interrupts, 9-22

memory map, 9-9

modes of operation, 9-3

overview, 1-14

page mode and logical bank retention, 9-45

performance monitor events, 19-16

by acronym, see Register Index

configuration registers, 9-10-9-17

error handling registers, 9-19-9-25

error injection registers, 9-17-9-19

SDRAM operation, 9-30

address multiplexing, 9-31

initialization sequence, 9-50

JEDEC standard interface commands, 9-32

mode-set command timing, 9-38

organizations supported, 9-31

refresh operation, 9-41

power-saving modes, 9-43

timing, 9-42

registered DIMM mode, 9-39

timing, 9-34

write timing adjustments, 9-40

self-refresh in sleep mode, 9-44

signals summary, 9-3

see also Signals, debug

and watchpoint monitor/trace buffer block diagram, 20-1

DDR signal selection (POR)

ECC pins used for debug, 4-21

DDR source ID debug modes, 20-4, 20-26

source ID on debug signals, 20-28

source ID on ECC pins, 20-28

DDR/LBC signal selection (POR), 4-20

e500 core registers, 6-42-6-48

features, 20-3

functional description, 20-26

LBC source ID debug mode, 13-4, 20-4, 20-26

memory map/register definition, 20-10

modes of operation (set at POR), 20-3

overview, 20-2

PCI/PCI-X

debug configuration (POR), 4-20

source ID debug mode, 20-5, 20-26

performance monitor events, 19-26

POR status (global utilities), 18-9

READY negation, 4-2

software debug

context ID registers, 20-24

trace buffer, see Trace buffer

watchpoint, see Watchpoint monitor

DEC (decrementer register), see e500 core, registers

DECAR (decrementer auto-reload register), see e500 core,

registers

Delay-locked loops (DLLs)

DDR DLL control, 18-19

LBC DLL control, 18-20

DMA channel 2 and 3 signal select, 18-12

DMA controller

block diagram, 15-1

channel operation, 15-28

bandwidth control, 15-36

channel abort, 15-35

channel state, 15-36

stride size and distance, 15-36

descriptor formats, 15-37

error handling, 15-37

features, 15-2

functional description, 15-28

interrupts, 15-10-15-14, 15-16, 15-24, 15-27, 15-37

limitations and restrictions, 15-40

memory map/register definition, 15-6

modes of operation, 15-2

basic mode transfer, 15-29

basic chaining mode, 15-31

basic chaining single-write start mode, 15-31

basic direct mode, 15-29

basic direct single-write start mode, 15-30

channel continue mode for cascading transfer chains,

15-34

basic channel continue mode, 15-35

extended mode, 15-35

extended DMA mode transfer, 15-32

extended chaining mode, 15-32

extended chaining single-write start mode, 15-33

extended direct mode, 15-32

extended direct single-write start mode, 15-32

external control mode transfer, 15-33

MPC8540 Datasheet(PDF) 1281 Page - Freescale Semiconductor, Inc

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