MPC8540 datasheet(1284/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 2-6

Freescale Semiconductor

F–F

MCAR (machine check address register), 6-22

MCSR (machine check syndrome register), 6-23

MCSRR0 (machine check save/restore register 0), 6-21

MCSRR1 (machine check save/restore register 1), 6-22

MMUCFG (MMU configuration register), 6-35

MMUCSR0 (MMU control and status register 0), 6-34

MSR (machine state register), 6-12

PIDn (process ID registers 0–2), 5-27, 6-34

PIR (processor ID register), 6-14

PMCn (performance monitor counter registers 0–3),

5-30, 6-54

PMGC0 (performance monitor global control register 0),

5-30, 6-52

PMLCan (performance monitor local control registers

a0–a3), 5-30, 6-52

PMLCbn (performance monitor local control registers

b0–b3), 5-30, 6-53

PVR (processor version register), 5-4, 6-14

SPEFSCR (signal processing and embedded

floating-point status and control register), 6-48

SPRGn (software-use registers 0–7), 6-24

SRR0 (save/restore register 0), 6-18

SRR1 (save/restore register 1), 6-18

SVR (system version register), 5-4, 6-14

TBL (time base lower register), 6-17

TBU (time base upper register), 6-17

TCR (timer control register), 6-15

TLB0CFG (TLB0 configuration register), 6-35

TLB1CFG (TLB1 configuration register), 6-36

TSR (timer status register), 6-16

UPMCn (user performance monitor counter registers

0–3), 5-30, 6-54

UPMGC0 (user performance monitor global control

UPMLCan (user performance monitor local control

registers a0–a3), 5-30, 6-52

UPMLCbn (user performance monitor local control

registers b0–b3), 5-30, 6-53

USPRG0 (user software-use register 0), 6-24

XER (integer exception register), 6-8

signal processing engine (SPE)

registers, 6-48

single-precision floating-point (SPFP) instructions, 5-12

software-use SPRs, 6-24

time base

RTC (real time clock) signal options, 4-3, 4-25

timer registers, 6-15-6-18

translation lookaside buffers (TLBs), see e500 core,

memory management unit (MMU)

EC_GTX_CLK125 (TSEC gigabit transmit 125 MHz source)

signals, 14-10

EC_MDC (TSEC management data clock) signals, 14-11

EC_MDIO (TSEC management data input/output) signals,

14-11

Error handling

DDR, 9-19-9-25, 9-48

DMA, 15-37

DUART, 12-3, 12-23

framing error, 12-9, 12-16, 12-21, 12-22, 12-23

overrun error, 12-23

parity error, 12-23

ECM

error handling registers, 8-5-8-8

FEC, 21-61-21-63

2C interface

boot sequencer mode, 11-17, 11-18

L2 cache/SRAM, 7-35

error handling registers, 7-12

error injection, 7-13

LBC

transfer error registers, 13-26-13-30

PCI/PCI-X

address/data parity, 16-66, 16-78, 16-79

error management registers, 16-28-16-35

reporting, 16-79

PERR and SERR signals, 16-79, 16-96

target-initiated termination, 16-65

retry transactions, 16-66

target-abort, 16-66

target-disconnect, 16-66

PCI-X, 16-96

address/data parity, 16-96

reporting, 16-96

RapidIO

see RapidIO controller, error handling

TSEC, 14-123-14-124

ESR (exception syndrome register), see e500 core, registers

External system configuration

POR (LAD[0:31]) status, 4-23, 18-9

External writes, see L2 cache/SRAM, stashing

Fast Ethernet controller, see FEC

Features, overview of device features, 1-2

FEC controller

block diagram, 21-5

buffer descriptors, 21-63

receive buffer descriptor (RxBD), 21-67

transmit data buffer descriptor (TxBD), 21-65

channel operation, 21-49

flow control, 21-59

frame reception, 21-53

frame recognition, 21-54

destination address recognition, 21-55

MPC8540 Datasheet(PDF) 1284 Page - Freescale Semiconductor, Inc

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