MPC8540 datasheet(1288/1302 Pages) FREESCALE

1288 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 2-10

Freescale Semiconductor

J–L

FEC, 21-59-21-60

interrupt registers, 21-13-21-18

2C interface

calling address match condition, 11-5

flowchart for interrupt service routine, 11-23

interrupt after transfer, 11-21

interrupt enable bit (I2CCR[MIEN]), 11-7

interrupt on START, 11-21

interrupt pending status bit (I2CSR[MIF]), 11-9

interrupt-driven byte-to-byte transfers, 11-2

read of last byte, 11-22

slave mode interrupt service routine guidelines, 11-23

for slave transmitter routine, 11-23

loss of arbitration, 11-23

IRQ[9:11] signal select, 18-12, 18-29

LBC interrupt register, 13-28

PCI/PCI-X error enable register, 16-31

performance monitor (PIC), 19-20

power management and interrupts (global utilities), 18-27

RapidIO

message unit

doorbell controller interrupts, 17-121

inbox controller interrupts, 17-118

outbox controller interrupts, 17-116

port notification/fatal error interrupt enable register

(PNFEIER), 17-49

see also Signals, JTAG, 20-6

L1CFG0 (L1 cache configuration register 0), see e500 core,

registers

L1CFG1 (L1 cache configuration register 1), see e500 core,

registers

L1CSR0 (L1 cache status and control register 0), see e500

core, registers

L1CSR1 (L1 cache status and control register 1), see e500

core, registers

L2 cache/SRAM

allocation of lines, 7-29

block diagram, 7-1

coherency rules, 7-22

configuration and organization, 7-3

error handling

ECC errors, 7-35

tag parity errors, 7-36

error handling registers, 7-12

error injection, 7-13

external writes, see stashing

flash clearing, instruction and data locks, 7-27

initialization/application information, 7-34-7-36

invalidation, 7-30

locking

clearing locks on selected lines, 7-26

entire, 7-25

programmed memory ranges, 7-25

selected lines, 7-25

with stale data, 7-27

memory map/register definition, 7-6

memory-mapped SRAM

coherency rules, 7-24

memory-mapped windows, 2-4

operation, 7-29

organization, 7-3

overview, 1-12, 7-1

performance monitor events, 19-26

PLRU bit update considerations, 7-28

replacement policy, 7-27

SRAM features, 7-2

stashing, 7-21

state transitions, 7-30

due to core-initiated transactions, 7-31

due to system-initiated transactions, 7-33

timing, 7-21

LA[27:31] (LBC non-multiplexed address) signals, 13-7

LAD[0:31] (LBC multiplexed address/data) signals, 13-8

LALE (LBC external address latch enable) signal, 13-6,

13-35

LBCTL (LBC data buffer control) signal, 13-7, 13-37

LBS[0:3] (LBC UPM byte select) signals, 13-6

LCK[0:2] (LBC clock) signals, 13-8

LCKE (LBC clock enable) signal, 13-8

LCS[0:7] (LBC chip select) signals, 13-6

LCS[5:7] signal select

global utilities, 18-12

LCS0 (LBC chip select 0) signal, 13-50

LDP[0:3] (LBC data parity) signals, 13-8, 13-38

MPC8540 Datasheet(PDF) 1288 Page - Freescale Semiconductor, Inc

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