MPC8540 datasheet(1289/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 2-11

LGPL0 (LBC GP line 0) signal, 13-6

LGPL1 (LBC GP line 1) signal, 13-6

LGPL2 (LBC GP line 2) signal, 13-6

LGPL3 (LBC GP line 3) signal, 13-7

LGPL4 (LBC GP line 4) signal, 13-7

LGPL5 (LBC GP line 5) signal, 13-7

LGTA (LBC GPCM transfer acknowledge) signal, 13-7,

13-49

Local access windows, 2-3-2-9

ATMUs, see Address translation and mapping units

(ATMUs)

configuring local access windows, 2-7

distinguishing local access windows from other mapping

functions, 2-8

illegal interactions

between inbound ATMUs and local access windows, 2-9

between local access windows and DDR SDRAM chip

selects, 2-8

L2 cache/SRAM window interactions, 2-4

precedence if overlapping among themselves, 2-7

precedence if overlapping with L2 cache/SRAM windows,

2-4

registers, 2-6-2-7

by acronym, see Register Index

Local address map, 1-20

see also Local access windows

Local bus controller (LBC)

address and address space checking, 13-34

address mask field—option registers, 13-13

atomic bus operations, 13-37

block diagram, 13-1

boot chip-select operation, 13-50

bus monitor, 13-38

bus turnaround, 13-87

additional address phases (UPM cycles), 13-88

address following read, 13-87

read data following address, 13-88

read-modify-write cycle (parity), 13-88

clocks and clock ratios, 13-4

clock ratio register (LCRR), 13-32

configuration

LBC configuration register (LBCR), 13-31

debug mode

signal selection (POR), 4-20

source and target ID, 20-4, 20-26

DLL control (global utilities), 18-20

DSP hosts (interface to), 13-103

MSC8101 HDI16 interface, 13-103

MSC8102 DSI interface, 13-107

TI TMS320Cxxxx interface, 13-118

error handling

transfer error registers, 13-26-13-30

external access termination (LGTA), 13-49

features, 13-2

functional description, 13-33

general-purpose chip-select machine (GPCM), 13-38

chip-select and write enable negation timing, 13-44

chip-select assertion timing, 13-44

extended hold time on read accesses, 13-48

GPCM mode

registers, 13-14

output enable timing, 13-48

programmable wait state configuration, 13-44

relaxed timing, 13-45

timing configuration, 13-39

initialization/application information, 13-84-13-121

interrupts

transfer error interrupt enable register (LTEIR), 13-28

LCS[5:7] signal select, 18-12, 18-29

memory map/register definition, 13-9

memory refresh timer prescaler, 13-21

modes of operation, 13-3

bus clock and clock ratios, 13-4

GPCM mode, registers, 13-14

power-down mode, 13-4

SDRAM mode, registers, 13-17

source ID debug mode, 13-4

UPM mode, registers, 13-16

output hold configuration (POR), 4-22

overview, 1-17, 13-2

parity generation and checking, 13-38, 13-101

performance monitor events, 19-25

peripherals, 13-84

GPCM timing, 13-86

hierarchy for very high speeds, 13-85

hierarchy on the local bus, 13-84

multiplexed address/data, 13-84

port sizes, 13-88

references, other, 13-4

by acronym, see Register Index

SDRAM interface, 13-51-13-61, 13-90

address multiplexing, 13-54

basic capabilities, 13-90

commands (Intel PC133 and JEDEC), 13-52

configurations supported, 13-51

device-specific parameters, 13-55

limitations, 13-92-13-100

maximum SDRAM supported, 13-91

page hit checking, 13-53

page management, 13-54

parity support, 13-101

power-on initialization, 13-52

refresh, 13-61

MPC8540 Datasheet(PDF) 1289 Page - Freescale Semiconductor, Inc

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