MPC8540 datasheet(1291/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 2-13

illegal interaction between local access windows and

DDR SDRAM chip selects, 2-8

debug, watchpoint, and trace buffer registers, 20-10

device memory map

address translation and mapping, 2-3

overview and example, 2-1

DMA, 15-6

DUART, 12-4

ECM, 8-2

FEC, 21-9

global utilities, 18-3

2C, 11-4

interrupt controller (PIC), 10-9

L2 cache/SRAM, 7-6

LBC, 13-9

PCI/PCI-X, 16-15

performance monitor, 19-3

RapidIO, 17-9

TSEC, 14-13

Memory space

PCI/PCI-X addressing, 16-59

Memory target queue

performance monitor events, 19-17

Memory unit, see L2 cache/SRAM

Message interrupts, see Interrupt controller (PIC), message

interrupts

Message unit

see RapidIO controller, message unit, 17-109

MMUCFG (MMU configuration register), see e500 core,

registers

MMUCSR0 (MMU control and status register 0), see e500

core, registers

MRAS (DDR row address strobe) signal, 9-7

MSR (machine state register), see e500 core, registers

MSRCID[0:4] (DDR/LBC debug source ID) signals, 4-20,

13-9, 20-4, 20-8

MSYNC_IN (DDR DRAM DLL synchronization input)

signal, 9-8

MSYNC_OUT (DDR DRAM DLL synchronization output)

signal, 9-8

MWE (DDR write enable) signal, 9-7

Nap mode, 1-19, 18-23

see also Global utilities, power management

OCeaN switch fabric, 1-20

On-chip memory

as L2 cache, 1-13

as memory-mapped SRAM, 1-13

see also L2 cache/SRAM

Output hold

see Power-on reset (POR), configuration

Page hit checking (LBC SDRAM), 13-53

Page management (LBC SDRAM), 13-54

PCI Local Bus Specification configuration registers

see PCI/PCI-X controller, register descriptions

PCI/PCI-X controller

64-bit/32-bit bus, 16-6

address bus decoding, 16-59

address translation and mapping unit (ATMU)

inbound windows (4), 2-9, 16-24

outbound windows (4), 16-20

arbiter configuration (POR), 4-19, 16-5, 16-6

block diagram, 16-1

burst operations

cache wrap mode, 16-59

linear incrementing, 16-59

bus arbitration, 16-5, 16-53

bus protocol, 16-56

burst operation, 16-57

command encodings, 16-57

PCI-X-specific protocol, see PCI/PCI-X controller,

PCI-X operation

clocking, 16-57, 16-62

commands

command register, 16-38, 16-72

encodings, 16-57

interrupt-acknowledge transactions, 16-76

PCI-X encodings, 16-82

special-cycle, 16-77

configuration cycles, 16-70, 16-71

configuration space addressing, 16-60

host access example, 16-72

type 0 configuration translation, 16-74

type 1 configuration translation, 16-76

data bus width (POR), 4-19

debug configuration (POR), 4-20

debug mode

source and target ID (PCI_AD[62:58]), 20-5, 20-26

error handling, 16-79

address/data parity, 16-66, 16-78, 16-79

detection and reporting, 16-78, 16-96

error management registers, 16-28-16-35

PCI-X, 16-96

address/data parity, 16-96

reporting

PERR and SERR signals, 16-79, 16-96

target-initiated termination, 16-65

retry transactions, 16-66

MPC8540 Datasheet(PDF) 1291 Page - Freescale Semiconductor, Inc

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