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MPC8540 Datasheet(PDF) 1292 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1292 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Index 2-14
Freescale Semiconductor
P–P
target-abort, 16-66
target-disconnect, 16-66
features, 16-4
functional description, 16-53
host/agent configuration (POR), 4-14
I/O impedance (POR), 4-19
I/O space addressing, 16-60
initialization/application information, 16-99-16-101
initiator/master operation, 16-3
interrupts
error enable register, 16-31
latency timer, 16-43, 16-66, 16-72
memory map/register definition, 16-15
memory space addressing, 16-59
modes of operation, 16-5
agent configuration lock mode, 16-100
agent mode, 16-100
cache wrap mode, 16-59
host mode, 16-100
linear incrementing, 16-59
PCI-X mode
selection (POR), 4-20
output hold configuration (POR), 4-21
overview, 1-18, 16-2
PCI-X operation
attribute phase, 16-83
bus protocol, 16-81-16-98
command encodings, 16-82
configuration, 16-93
nonposted writes, 16-100
outbound read transaction alignment, 16-101
terminology, 16-81
transactions, 16-84-16-88, 16-89-16-92
completer attributes, 16-91
completion address, 16-90
split response, 16-89
split transactions, 16-89-16-92
wait state and terminations rules, 16-88
performance monitor events
common events, 19-20
PCI-specific events, 19-22
POR configuration, 16-99
power management
special-cycle operations, 16-77
register descriptions
configuration header registers, 16-36-16-53, 16-72
32-bit memory base address register, 16-44
64-bit high memory base address register, 16-46
64-bit low memory base address register, 16-45
arbiter configuration register (PBACR), 16-50
base address registers, 16-43-16-46
base class code register, 16-42
bus function register (PBFR), 16-49
bus status register, 16-40, 16-61, 16-65
cache line size register, 16-43
capabilities pointer register, 16-47
command register, 16-38, 16-72
configuration and status register base address
(PCSRBAR), 16-44
device ID register, 16-38
interrupt line register, 16-47
interrupt pin register, 16-48
latency timer register, 16-43
maximum grant (MAX GNT) register, 16-48
maximum latency (MAX LAT) register, 16-49
PCI-X capability pointer register, 16-51
PCI-X command register, 16-52
PCI-X next capabilities ID register, 16-51
PCI-X status register, 16-52
programming interface register, 16-41
revision ID register, 16-41
subclass code register, 16-42
subsystem ID register, 16-46
subsystem vendor ID register, 16-46
vendor ID register, 16-37
memory-mapped registers, 16-15
ATMU inbound registers, 16-24-16-28
ATMU outbound registers, 16-20-16-24
by acronym, see Register Index
configuration access registers, 16-18-16-20
error management registers, 16-28-16-35
signals summary, 16-7
see also Signals, PCI/PCI-X
target/slave operation, 16-4
target-abort termination, 16-66
target-disconnect cycles, 16-4, 16-66
target-initiated termination
target-abort error, 16-66
target-disconnect, 16-4, 16-66
transactions
dual address cycles (DACs), 16-68
fast back-to-back transactions, 16-68
interrupt-acknowledge transactions, 16-76
PCI-X, see PCI/PCI-X controller, PCI-X operation
read transactions, 16-62
retry transactions, 16-66
special-cycle transactions, 16-77
timing diagrams, 16-61
transaction termination, 16-64
bus status register, termination status, 16-66
completion, 16-65
master-abort termination, 16-65
master-initiated, 16-65
target-initiated, 16-65, 16-66



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