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MPC8540 Datasheet(PDF) 1293 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1293 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
Freescale Semiconductor
Index 2-15
timeout, 16-65
write transactions, 16-61, 16-63
turnaround cycle, 16-61
PCI_AD[47:40] signals as GP I/O, see Global utilities,
general-purpose I/O signals
PCI_AD[62:58] (high-order PCI address) signals as debug,
20-4, 20-8
PCI_AD[63:0] (PCI address/data bus) signals, 16-8, 16-59
PCI_C/BE[7:0] (PCI command/byte enable) signals, 16-9,
16-57, 16-60, 16-61, 16-78
PCI_DEVSEL (PCI device select) signal, 16-60
PCI_FRAME (PCI frame) signal, 16-57
PCI_GNT[4:0] (PCI bus grant) signals, 16-10, 16-54
PCI_IDSEL (PCI initialization device) signal, 16-10
PCI_IRDY (PCI intitiator ready) signal, 16-11, 16-57
PCI_PAR (PCI parity) signal, 16-11, 16-78
PCI_PAR64 (PCI upper DWORD parity) signal, 16-12
PCI_PERR (PCI parity error) signal, 16-12, 16-79, 16-96
PCI_REQ[4:0] (PCI bus request) signals, 16-13, 16-54
PCI_REQ64 (PCI 64-bit transaction request) signal, 16-13
PCI_SERR (PCI system error) signal, 16-13, 16-79, 16-96
PCI_STOP (PCI stop) signal, 16-14, 16-61
PCI_TRDY (PCI target ready) signal, 16-14, 16-57
PCI_TRDY (target ready) signal, 16-65
Performance monitor (device)
block diagram, 19-2
burstiness, 19-13, 19-28
control registers, 19-5-19-9
counters (PMCn)
chaining, 19-12
registers, 19-9
triggering, 19-12
event counting, 19-11
events, 19-15-19-27
chaining, 19-27
DDR controller, 19-16
debug, 19-26
DMA controller, 19-18
DUART, 19-27
e500 coherency module (ECM), 19-18
interrupt controller (PIC), 19-20
L2 cache/SRAM, 19-26
local bus controller (LBC), 19-25
memory target queue, 19-17
PCI/PCI-X common events, 19-20
PCI-specific events, 19-22
RapidIO controller, 19-17
TSEC1, 19-22, 19-23
TSEC2, 19-24
events triggered by watchpoint monitor, 20-29
examples, 19-27
burstiness event, 19-13
burstiness event counting, 19-28
simple event counting, 19-27, 19-28
threshold event counting, 19-28
triggering event counting, 19-28
external signals, 19-3
features, 19-3
functional description, 19-10
interrupts, 19-10
interrupts (from PIC) to generate events, 10-28
masking interrupts (from PIC), 10-28
memory map/register definition, 19-3
overflow indication on TRIG_OUT, 20-26
overview, 19-1
threshold events, 19-11
Performance monitor (e500 core)
counter registers, 5-30
Phase-locked loops (PLLs)
POR status (global utilities), 18-4
PIDn (process ID registers 0–2), see e500 core, registers
PIR (processor ID register), see e500 core, registers
PMCn (performance monitor counter registers 0–3), see e500
core, registers
PMGC0 (performance monitor global control register 0), see
e500 core, registers
PMLCan (performance monitor local control registers
a0–a3), see e500 core, registers
PMLCbn (performance monitor local control registers
b0–b3), see e500 core, registers
Power management
block disable
block disable control (DEVDISR), 18-13, 18-22
LBC, 13-4
DDR interface, 9-43
device low-power modes, 18-21-18-28
control and status register (POWMGTCSR), 18-15
READY negation, 4-2
interrupts that cause wake-up, 10-4
overview, 1-19
PCI special-cycle operations, 16-77
see also Global utilities, power management
Power-on reset (POR)
configuration
boot ROM location, 4-14
boot sequencer configuration, 4-16
clock
e500 core PLL ratio, 4-13
system/CCB PLL ratio, 4-12
CPU boot configuration, 4-15
DDR debug mode (ECC pins used for debug), 4-21, 20-3
general-purpose (external system)
configuration—LAD[0:31] (GPPORCR), 4-23
host/agent configuration (PCI and RapidIO), 4-14



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