MPC8540 datasheet(1294/1302 Pages) FREESCALE

1294 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 2-16

Freescale Semiconductor

R–R

memory debug select (DDR or LBC), 4-20, 20-3

output hold

LBC output hold, 4-22

PCI/PCI-X output hold, 4-21

PCI data bus width, 4-19

PCI debug configuration, 4-20, 20-3

PCI I/O impedance, 4-19

PCI/PCI-X arbiter configuration, 4-19

PCI/PCI-X, modes of operation, 16-99

PCI-X mode selection, 4-20

RapidIO device ID, 4-18

RapidIO transmit clock source, 4-18

TSEC data width, 4-16

TSEC1 protocol, 4-17

TSEC2 protocol, 4-17

configuration reporting

global utilities, 18-4, 18-5, 18-6, 18-7, 18-9

debug modes summary, 20-3

hard reset, 4-9

output signal states during reset, 3-17

reset configuration signals, 3-15

sequence of events, 4-9

and READY signal, 4-2, 4-10

Processor version (PVR), 18-17

Protocols

PCI, see PCI/PCI-X controller, bus protocol

PVR (processor version register), see e500 core, registers

RapidIO controller

accept-all mode, 17-6

address translation and mapping unit (ATMU), 17-106

inbound ATMU translation, 2-9, 17-107

bypass mode, 17-108

errors, boundary crossing, 17-109

inbound windows (4 plus default), 17-40-17-43

LCSRBAR window, 17-108

special transactions and requirements, 17-108

outbound ATMU translation, 17-106

bypass mode, 17-107

outbound windows (8 plus default), 17-37-17-40

special transactions and requirements, 17-107

assembly identity capability, 17-14

clocks

clock selection, transmit clock source (POR), 4-18, 17-8

operation, 4-24

command and status registers, 17-22-17-34

configuration

configuration/error injection registers, 17-34-17-36

CRC checking modes, 17-5

device ID (POR), 4-18

error handling, 17-102

error checking disable mode, 17-6

error handling registers, 17-43-17-65

message unit

doorbell error response conditions, 17-121

inbox error response conditions, 17-118

special outbox error response conditions, 17-117

packet error packet register 1 (PEPR1)

packet error capture registers (9 types) (PECR1Tx),

17-53-17-58

packet error packet register 2 (PEPR2)

packet error capture registers (9 types) (PECR2Tx),

17-58-17-61

features, 17-4

features not implemented, 17-5

functional description, 17-83

functionality of RapidIO interface, 17-89

functionality lists

8/16 LP-LVDS layer, 17-91

logical layer, 17-100

source transaction support list, 17-101

host/agent configuration (POR), 4-14

initialization/application information, 17-122

interrupts

message unit

doorbell controller interrupts, 17-121

inbox controller interrupts, 17-118

outbox controller interrupts, 17-116

port notification/fatal error interrupt enable register

(PNFEIER), 17-49

low-voltage differential signaling, see RapidIO,

functionality lists, 8/16 LP-LVDS

mailbox command and status, 17-22

memory map/register definition, 17-9

message unit

data message controller, 17-111

doorbell message controller, 17-119

doorbell controller interrupts, 17-121

doorbell queue entry format, 17-120

error response conditions, 17-121

inbound doorbell reception, 17-120

retry response conditions, 17-121

features, 17-110

inbox controller operation, 17-117

data message controller limitations and restrictions,

17-119

error response conditions, 17-118

inbox controller interrupts, 17-118

retry response conditions, 17-118

messaging, description, 17-111

modes of operation, 17-111

outbound descriptors, 17-72

outbox controller operation, 17-111

MPC8540 Datasheet(PDF) 1294 Page - Freescale Semiconductor, Inc

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