MPC8540 datasheet(1298/1302 Pages) FREESCALE

1298 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 2-20

Freescale Semiconductor

T–T

EC_GTX_CLK125 (TSEC gigabit transmit 125 MHz

source), 14-10

EC_MDC (TSEC management data clock), 14-11

EC_MDIO (TSEC management data input/output),

14-11

TSECn_COL (TSEC 1–2 collision input), 14-10

TSECn_CRS (TSEC 1–2 carrier sense input), 14-10

TSECn_GTX_CLK (TSEC 1–2 gigabit transmit clock),

14-10

TSECn_RX_CLK (TSEC 1–2 receive clock), 14-11

TSECn_RX_DV (TSEC 1–2 receive data valid), 14-11

TSECn_RX_ER (TSEC 1–2 receive error), 14-12

TSECn_RXD[7:0] (TSEC 1–2 receive data in), 14-11

TSECn_TX_CLK (TSEC 1–2 transmit clock in), 14-12

TSECn_TX_EN (TSEC 1–2 transmit data valid in),

14-12

TSECn_TX_ER (TSEC 1–2 transmit error in), 14-12

TSECn_TXD[7:0] (TSEC 1–2 transmit data out), 14-12

watchpoint monitor

TRIG_IN (watchpoint trigger in), 20-8, 20-12, 20-18

TRIG_OUT (watchpoint trigger out), 20-9, 20-25

Sleep mode, 1-19, 18-24, 18-28

see also Global utilities, power management

Snooping

power management and snooping (global utilities), 18-28

Soft reset and reconfiguring for FEC, 21-51

Soft reset and reconfiguring for TSEC, 14-112

SPEFSCR (signal processing and embedded floating-point

status and control register), see e500 core, registers

SPRGn (software-use registers 0–7), see e500 core, registers

SRAM, see L2 cache/SRAM, 7-22

SRESET (soft reset) signal, 4-2, 4-9

SRR0 (save/restore register 0), see e500 core, registers

SRR1 (save/restore register 1), see e500 core, registers

Stashing, see L2 cache/SRAM, stashing, 7-21

SVR (system version register), see e500 core, registers

SYSCLK (system clock input) signal, 4-3

System version (SVR), 18-18

TA (LBC data transfer acknowledge) signal, 13-36

Target-disconnect, see PCI/PCI-X controller

TBL (time base lower register), see e500 core, registers

TBU (time base upper register), see e500 core, registers

TCK (JTAG test clock) signal, 20-9

TCR (timer control register), see e500 core, registers

TDI (JTAG test data input) signal, 20-9

TDO (JTAG test data output) signal, 20-9

Termination

PCI/PCI-X, termination of PCI transactions, 16-64

Test interface, see JTAG test access port

TEST_SEL (factory test) signal, 20-10

THERM[0:1] (thermal resistor access) signals, 20-10

Three-speed Ethernet controller, see TSEC

Timing diagrams

PCI/PCI-X transactions

TLB0CFG (TLB0 configuration register), see e500 core,

registers

TLB1CFG (TLB1 configuration register), see e500 core,

registers

TMS (JTAG test mode select) signal, 20-9

Trace buffer

and watchpoint monitor, block diagram, 20-1

as a second watchpoint monitor, 20-29

functional description, 20-29-20-32

initialization, 20-33

modes of triggering and arming, 20-5

overview, 20-2

by acronym, see Register Index

MPC8540 Datasheet(PDF) 1298 Page - Freescale Semiconductor, Inc

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