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MPC8540 Datasheet(PDF) 1296 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1296 Page - Freescale Semiconductor, Inc |
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1296 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Index 2-18 Freescale Semiconductor S–S block header command and status registers, 17-27-17-34 command and status registers, 17-22-17-34 implementation registers, 17-34-17-65 ATMU, 17-36-17-43 configuration/error injection, 17-34-17-36 error handling, 17-43-17-65 message unit registers, 17-65-17-83 doorbell registers, 17-77-17-81 inbound message registers, 17-72-17-76 outbound descriptors, 17-72 outbound message registers, 17-65-17-72 port-write registers, 17-81-17-83 system version register (SVR), 18-18 trace buffer, 20-16-20-23 trigger out source register, 20-25 TSEC FIFO control and status registers, 14-30-14-33 general control and status registers, 14-20-14-30 hash function registers, 14-87-14-89 MAC registers, 14-46-14-60 MIB registers, 14-60-14-87 receive control and status registers, 14-40-14-46 ten-bit interface (TBI) registers, 14-91-14-103 transmit control and status registers, 14-33-14-40 watchpoint monitor, 20-11-20-16 Reset core reset through PIC register, 10-18, 10-46 hard reset actions, 4-9 operations, 4-8 power-on reset (POR) configuration, see Power-on reset (POR), configuration sequence of events, 4-9 signals summary, 4-2 see also Signals, reset soft reset actions, 4-9 RIO_RCLK and RIO_RCLK (RapidIO receive clock and complement) signals, 17-8 RIO_RD[0:7] and RIO_RD[0:7] (RapidIO receive data and complement) signals, 17-8 RIO_RFRAME and RIO_RFRAME (RapidIO receive frame and complement) signals, 17-8 RIO_TCLK and RIO_TCLK (RapidIO transmit clock out and complement) signals, 17-8 RIO_TD[0:7] and RIO_TD[0:7] (RapidIO transmit data and complement) signals, 17-8 RIO_TFRAME and RIO_TFRAME (RapidIO transmit frame and complement) signals, 17-9 RIO_TX_CLK_IN and RIO_TX_CLK_IN (RapidIO transmit clock in and complement) signals, 17-9 RTC (real time clock) signal, 4-3, 4-25, 10-24, 10-25, 18-25 RTS, see DUART_RTS[0:1] S SCL (I 2C serial clock) signal, 11-3, 11-4 SDA (I 2C serial data) signal, 11-3, 11-4 SDRAM interface (LBC), 13-51-13-61 see also Local bus controller (LBC), SDRAM interface Serial data/clock, see I 2C interface, 11-1 Signals clock RTC (real time clock), 4-3, 4-25, 10-24, 10-25, 18-25 SYSCLK (system clock input), 4-3 complete signal listing alphabetical reference, 3-9 configuration signals, sampled at POR, 3-15 see also Power-on reset (POR) figure showing groupings, 3-1 output signal states at power-on reset, 3-17 reference by functional block, 3-4 DDR MA[0:14] (address bus), 9-6 MBA[0:1] (logical bank address), 9-6 MCAS (column address strobe), 9-6 MCK[0:5] (DDR clock output complements), 9-8 MCK[0:5] (DDR clock outputs), 9-8 MCKE (DDR clock enable), 9-8 MCS[0:3] (chip selects), 9-7 MDM[0:8] (SDRAM data output mask), 9-7 MDQS[0:8] (data bus strobes), 9-5, 9-27 MDVAL (debug mode data valid), 4-20, 20-4, 20-7 MECC[0:5] (error correcting code) as debug signals, 20-4, 20-8 MECC[0:7] (error correcting code), 4-21 MECC[0:7] (error correcting codes), 9-6 MRAS (row address strobe), 9-7 MSRCID[0:4] (debug source ID), 4-20, 20-4, 20-8 MSYNC_IN (DRAM DLL synchronization input), 9-8 MSYNC_OUT (DRAM DLL synchronization output), 9-8 MWE (write enable), 9-7 DMA DMA_DACK[0:3] (DMA acknowledge), 15-6 DMA_DDONE[0:3] (DMA done), 15-6 DMA_DREQ[0:3] (DMA request), 15-6 DUART UART_CTS[0:1] (DUART clear to send), 12-1, 12-3, 12-4 UART_RTS[0:1] (DUART request to send), 12-1, 12-3, 12-4 UART_SIN [0:1] (DUART transmitter serial data in), 12-3, 12-4 UART_SOUT [0:1] (DUART transmitter serial data out), 12-3, 12-4 FEC |
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