MPC8540 datasheet(1297/1302 Pages) FREESCALE

1297 / 1302 page

S–S

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 2-19

FEC_COL (FEC collision input), 21-8

FEC_CRS (FEC carrier sense input), 21-8

FEC_RX_CLK (FEC receive clock), 21-8

FEC_RX_DV (FEC receive data valid), 21-8

FEC_RX_ER (FEC receive error), 21-8

FEC_RXD[3:0] (FEC receive data in), 21-8

FEC_TX_CLK (FEC transmit clock in), 21-8

FEC_TX_EN (FEC transmit data valid in), 21-8

FEC_TX_ER (FEC transmit error in), 21-9

FEC_TXD[3:0] (FEC transmit data out), 21-8

global utilities

ASLEEP, 18-2, 18-24

CKSTP_IN (checkstop in), 18-3

CKSTP_OUT (checkstop out), 18-3

CLK_OUT, 18-3, 18-18

SCL (serial clock), 11-3, 11-4

SDA (serial data), 11-3, 11-4

JTAG

TCK (JTAG test clock), 20-9

TDI (JTAG test data input), 20-9

TDO (JTAG test data output), 20-9

TMS (JTAG test mode select), 20-9

TRST (JTAG test reset), 20-10

LBC

LA[27:31] (non-multiplexed address), 13-7

LAD[0:31] (multiplexed address/data), 13-8

LALE (external address latch enable), 13-6, 13-35

LBCTL (data buffer control), 13-7, 13-37

LBS[0:3] (UPM byte select), 13-6

LCK[0:2] (clock), 13-8

LCKE (clock enable), 13-8

LCS[0:7] (chip select), 13-6

LCS0 (LBC chip select 0), 13-50

LDP[0:3] (data parity), 13-8, 13-38

LGPL0 (GP line 0), 13-6

LGPL1 (GP line 1), 13-6

LGPL2 (GP line 2), 13-6

LGPL3 (GP line 3), 13-7

LGPL4 (GP line 4), 13-7

LGPL5 (GP line 5), 13-7

LGTA (GPCM transfer acknowledge), 13-7, 13-49

LOE (GPCM output enable), 13-6

LPBSE (parity byte select), 13-7

LSDA10 (SDRAM A10), 13-6

LSDCAS (SDRAM CAS), 13-7

LSDDQM[0:3] (SDRAM data mask), 13-6

LSDRAS (SDRAM RAS), 13-6

LSDWE (SDRAM write enable), 13-6

LSYNC_IN (DLL synchronization in), 13-8

LSYNC_OUT (DLL synchronization out), 13-8

LWE[0:3] (GPCM write enable), 13-6

MDVAL (debug mode data valid), 4-20, 13-9, 20-4, 20-7

MSRCID[0:4] (debug source ID), 4-20, 13-9, 20-4, 20-8

TA (data transfer acknowledge), 13-36

UPWAIT (UPM wait), 13-7, 13-63

other

TEST_SEL (factory test), 20-10

THERM[0:1] (thermal resistor access), 20-10

PCI/PCI-X

PCI_AD[62:58] (high-order PCI address)

as debug signals, 20-4, 20-8

PCI_AD[63:0] (address/data bus), 16-8, 16-59

PCI_C/BE[7:0] (command/byte enable), 16-9, 16-57,

16-60, 16-61, 16-78

PCI_DEVSEL (device select), 16-60

PCI_FRAME (frame), 16-57

PCI_GNT[4:0] (bus grant), 16-10, 16-54

PCI_IDSEL (initialization device), 16-10

PCI_IRDY (intitiator ready), 16-11, 16-57

PCI_PAR (parity), 16-11, 16-78

PCI_PAR64 (upper DWORD parity), 16-12

PCI_PERR (parity error), 16-12, 16-79, 16-96

PCI_REQ[4:0] (bus request), 16-13, 16-54

PCI_REQ64[4:0] (64-bit transaction request), 16-13

PCI_SERR (system error), 16-13, 16-79, 16-96

PCI_STOP (stop), 16-14, 16-61

PCI_TRDY (target ready), 16-14, 16-57

PIC

IRQ[0:11], 10-8

IRQ_OUT, 10-9, 10-26

MCP, 10-9

UDE, 10-9

RapidIO

RIO_RCLK and RIO_RCLK (receive clock and

complement), 17-8

RIO_RD[0:7] and RIO_RD[0:7] (receive data and

complements), 17-8

RIO_RFRAME and RIO_RFRAME (receive frame and

complement), 17-8

RIO_TCLK and RIO_TCLK (transmit clock out and

complement), 17-8

RIO_TD[0:7] and RIO_TD[0:7] (transmit data and

complement), 17-8

RIO_TFRAME and RIO_TFRAME (transmit frame and

complement), 17-9

RIO_TX_CLK_IN and RIO_TX_CLK_IN (transmit

clock in and complement), 17-9

reset

HRESET (hard reset), 4-2, 4-9

HRESET_REQ (hard reset request), 4-2, 11-17, 11-18

READY, 4-2, 20-25, 20-26

SRESET (soft reset), 4-2, 4-9

TSEC

MPC8540 Datasheet(PDF) 1297 Page - Freescale Semiconductor, Inc

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