MPC8540 datasheet(1295/1302 Pages) FREESCALE

1295 / 1302 page

R–R

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 2-17

chaining mode operation, 17-112

descriptor format, 17-115

direct mode operation, 17-112

interrupts, 17-116

special error case condition, 17-117

switching between modes, 17-115

overview, 1-19, 17-109

port-write controller

structure, 17-121

registers, see RapidIO controller, registers

modes of operation, 17-5

accept-all mode, 17-6

CRC checking modes, 17-5

error checking disable mode, 17-6

link response time-out disable mode, 17-6

output port driver disable mode, 17-6

output port enable mode, 17-6

packet response time-out disable mode, 17-6

transmit clock-select mode, 17-5

see also RapidIO controller, clocks, 17-5

overview, 1-18, 17-7

performance monitor events, 19-17

registers

architectural registers, 17-13-17-34

block header command and status registers,

17-27-17-34

command and status registers, 17-22-17-34

implementation registers, 17-34-17-65

ATMU, 17-36-17-43

configuration/error injection, 17-34-17-36

error handling, 17-43-17-65

message unit registers, 17-65-17-83

doorbell registers, 17-77-17-81

inbound message registers, 17-72-17-76

outbound descriptors, 17-72

outbound message registers, 17-65-17-72

port-write registers, 17-81-17-83

signals summary, 17-7

see also Signals, RapidIO

terminology, 17-4

transaction, packet, and control symbols, 17-83

READY signal, 4-2, 4-10, 20-25, 20-26

Registers

by acronym (memory-mapped registers)

see Register Index

configuration, control, and status, 2-10-2-16, 4-3

device-specific utilities, 2-15

general utilities, 2-13

programmable interrupt controller (PIC) space, 2-14

context ID, 20-24-20-25

DDR

configuration registers, 9-10-9-17

DLL control, 18-19

error handling registers, 9-19-9-25

error injection registers, 9-17-9-19

e500 core, see e500 core, registers

ECM, 8-3

FEC

FIFO control and status registers, 21-21-21-25

general control and status registers, 21-13-21-21

hash function registers, 21-45-21-46

MAC registers, 21-36-21-45

receive control and status registers, 21-31-21-36

transmit control and status registers, 21-25-21-31

global utilities, 18-4

POR boot mode status, 18-5

POR debug mode status, 18-9

POR device status, 18-7

POR external system configuration, 18-9

POR I/O impedance status, 18-6

POR PLL status, 18-4

2C interface, 11-4

L2 cache/SRAM registers, 7-6-7-20

LBC, 13-10

DLL control, 18-20

local access window registers

attributes registers (LAWAR0–LAWAR7), 2-6

base address registers (LAWBAR0–LAWBAR7), 2-6

PCI/PCI-X

configuration header registers, 16-36-16-53, 16-72

see also PCI/PCI-X controller, registers

memory-mapped registers

ATMU inbound registers, 16-24-16-28

ATMU outbound registers, 16-20-16-24

configuration access registers, 16-18-16-20

error management registers, 16-28-16-35

performance monitor (e500 core) counter registers, 5-30

performance monitor, descriptions, 19-3

PIC, 10-16

global registers, 10-16-10-20

global timer registers, 10-20-10-25

interrupt source configuration registers, 10-20-10-23,

10-32-10-37

message registers, 10-30-10-32

non-accessible registers

in-service register (ISR), 10-45

interrupt pending register (IPR), 10-43

interrupt request register (IRR), 10-43

per-CPU registers, 10-38-10-42

performance monitor mask registers, 10-28-10-30

summary registers, 10-26-10-28

processor version register (PVR), 18-17

RapidIO

architectural registers, 17-13-17-34

MPC8540 Datasheet(PDF) 1295 Page - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 1295 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL