MPC8540 datasheet(1290/1302 Pages) FREESCALE

1290 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 2-12

Freescale Semiconductor

M–M

SDRAM mode

registers, 13-17, 13-22

timing, 13-58

activate-to-read/write interval, 13-56

CAS latency, 13-56

external buffers, 13-57

MODE-SET commands, 13-60

precharge-to-activate interval, 13-55

refresh recovery, 13-57

refresh timing, 13-61

write recovery, 13-56

transactions, 13-60

signals summary, 13-5

see also Signals, LBC

UPM interfaces, 13-62-13-83

block diagram, 13-62

example interface, 13-78

extended hold time (reads), 13-77

programming the UPMs, 13-66

RAM array, 13-67

address multiplexing, 13-74

byte select signal timing, 13-72

chip select signal timing, 13-72

data timing, 13-75

general purpose signal timing, 13-73

LGPL[0:5] timing (LAST), 13-76

loop control, 13-73

RAM word definition, 13-68

REDO, 13-74

wait mechanism (WAEN), 13-76

signal timing, 13-66

synchronous UPWAIT (early transfer acknowledge),

13-77

UPM mode

registers, 13-16, 13-18

UPM requests, 13-63

exception requests, 13-66

memory access requests, 13-64

refresh timer requests, 13-65

software requests, 13-65

ZBT SRAM interface, 13-101

LOE (LBC GPCM output enable) signal, 13-6

Low-voltage differential signaling

see RapidIO, functionality lists, 8/16 LP-LVDS

LPBSE (LBC parity byte select) signal, 13-7

LR (link register), see e500 core, registers

LSDA10 (LBC SDRAM A10) signal, 13-6

LSDCAS (LBC SDRAM CAS) signal, 13-7

LSDDQM[0:3] (LBC SDRAM data mask) signal, 13-6

LSDRAS (LBC SDRAM RAS) signal, 13-6

LSDWE (LBC SDRAM write enable) signal, 13-6

LSYNC_IN (LBC DLL synchronization in) signal, 13-8

LSYNC_OUT (LBC DLL synchronization out) signal, 13-8

LWE[0:3] (LBC GPCM write enable) signals, 13-6

MA[0:14] (DDR address bus) signals, 9-6

MAC functionality

see FEC controller, MAC functionality

see TSEC, MAC functionality

Machine check

MCP (processor machine check) signal, 10-9

mcp summary register (MCPSUMR), 18-16

SRESET (soft reset) signal, 4-9

MAS0-MAS6 (MMU assist registers 0–6), see e500 core,

registers

MBA[0:1] (DDR logical bank address) signals, 9-6

MCAR (machine check address register), see e500 core,

registers

MCAS (DDR column address strobe) signal, 9-6

MCK[0:5] (DDR clock output complement) signals, 9-8

MCK[0:5] (DDR clock output) signals, 9-8

MCKE (DDR clock enable) signal, 9-8

MCP (processor machine check) signal, 10-9

MCS[0:3] (DDR chip select) signals, 9-7

MCSR (machine check syndrome register), see e500 core,

registers

MCSRR0 (machine check save/restore register 0), see e500

core, registers

MCSRR1 (machine check save/restore register 1), see e500

core, registers

MDM[0:8] (DDR SDRAM data output mask) signals, 9-7

MDQ[0:8] (DDR data bus strobe) signals, 9-5, 9-27

MDVAL (DDR/LBC debug mode data valid) signal, 4-20,

13-9, 20-4, 20-7

MECC[0:5] (DDR error correcting code) signals as debug,

20-4, 20-8

MECC[0:7] (DDR error correcting code) signals, 4-21, 9-6

Memory management unit (MMU), see e500 core, memory

management unit (MMU)

Memory maps

CCSR memory, 2-4

accessing CCSR memory from external masters, 2-11

CCSR and RapidIO registers, 2-15

CCSR map, complete list of memory-mapped registers

(by offset), 2-16

CCSR organization, 2-11

CCSR registers, 2-10-2-16

device-specific utilities, 2-15

general utilities registers, 2-13

programmable interrupt controller (PIC) space, 2-14

configuration, control, and status registers, 4-3

DDR controller, 9-9

MPC8540 Datasheet(PDF) 1290 Page - Freescale Semiconductor, Inc

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