MPC8540 datasheet(1286/1302 Pages) FREESCALE

1286 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Index 2-8

Freescale Semiconductor

H–I

nap mode, 18-23

power-down sequence, 18-24

sleep mode, 18-24, 18-28

software considerations, 18-28

processor version register (PVR), 18-17

by acronym, see Register Index

signals summary, 18-2

see also Local bus controller (LBC)

GPRs (general-purpose registers), see e500 core, registers

Hash table algorithm, see FEC controller, hash function

Hash table algorithm, see TSEC, hash function

HID0 (hardware implementation-dependent register 0), see

e500 core, registers

HID1 (hardware implementation-dependent register 1), see

e500 core, registers

Host/agent configuration (POR), PCI and RapidIO, 4-14

HRESET (hard reset) signal, 4-2, 4-9

HRESET_REQ (hard reset request) signal, 4-2, 11-17, 11-18

I/O impedance

LBC and PCI/PCI-X signals

control and status register (global utilities), 18-6

PCI/PCI-X interface (POR), 4-19

I/O requirements, 18-28

I/O space

PCI/PCI-X addressing, 16-60

2C controller

overview, 1-15

2C interface

arbitration

arbitration control, 11-14

loss of arbitration—forcing of slave mode, 11-23

procedure for arbitration, 11-14

block diagram, 11-1

boot sequencer

POR configuration, 4-16

boot sequencer mode, 11-2, 11-17-11-19

error condition behavior, 11-17, 11-18

calling address match condition, 11-5

clock control, 11-15

clock stretching, 11-17

clock synchronization, 11-16

input synchronization and digital filter, 11-16

master mode, 11-16

slave mode, 11-16

data transfer, 11-12

error handling

boot sequencer mode, 11-17, 11-18

features, 11-2

frequency divider

frequency divider register (I2CFDR), 11-5

functional description, 11-10

handshaking, 11-15

implementation details, 11-13

address compare, 11-14

control transfer, 11-13

transaction monitoring, 11-13

initialization/application information, 11-20-11-24

boot sequencer mode, see I

2C interface, boot sequencer

mode

generation of SCL when SDA low, 11-22

initialization sequence, 11-20

post-transfer software response, 11-21

repeated START generation, 11-22

START generation, 11-11, 11-21

STOP generation, 11-12, 11-22

interrupts

calling address match condition, 11-5

flowchart for interrupt service routine, 11-23

interrupt after transfer, 11-21

interrupt enable bit (I2CCR[MIEN]), 11-7

interrupt on START, 11-21

interrupt pending status bit (I2CSR[MIF]), 11-9

interrupt-driven byte-to-byte transfers, 11-2

read of last byte, 11-22

slave mode interrupt service routine guidelines, 11-23

for slave transmitter routine, 11-23

loss of arbitration, 11-23

memory map/register definition, 11-4

modes of operation, 11-2

boot sequencer mode, 11-2, 11-17-11-19

interrupt-driven byte-to-byte data transfer, 11-2

master mode, 11-2

slave mode, 11-2

overview, 11-2

by acronym, see Register Index

signals summary, 11-3

MPC8540 Datasheet(PDF) 1286 Page - Freescale Semiconductor, Inc

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