MPC8540 datasheet(1283/1302 Pages) FREESCALE

1283 / 1302 page

E–E

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 2-5

branch operations

registers, 6-9-6-11

branch target buffer (BTB)

registers, 6-25-6-27

branch target buffer (BTB) locking, 5-5

instructions, 5-13

cache line lock and unlock APU, 5-5

instructions, 5-12

clock multipliers, 5-11

see also Clocks, POR settings

computational operations

registers, 6-8-6-9

core complex bus (CCB), 5-9, 5-29

critical interrupts, 5-22

data cache, see e500 core, L1 caches

debug registers, 6-42-6-48

device implementation details, 5-33

exceptions and interrupt handling, 5-20

critical interrupts, 5-22

interrupt classes, 5-21

interrupt latencies (upper bound), 5-22

interrupt registers, 5-22

interrupt types, 5-21

execution units

load/store unit, 5-8

multiple-cycle unit (MU), 5-7

features, 5-5

Freescale Semiconductor Book E implementation

standards (EIS), 5-3

future compatibility warning and SPE APU, 1-9, 5-3, 5-33,

6-12

hardware implementation-dependent registers (HID0–1),

6-27-6-30

instruction flow, 5-14

branch detection and prediction, 5-14

execution pipeline, 5-15

instruction pipeline stages

complete and write-back, 5-17

decode/dispatch, 5-16

execute, 5-17

instruction fetch, 5-16

issue queues (BIQ, GIQ), 5-16

interrupts

registers, 6-18-6-24

sources, 10-4

L1 caches, 5-20

cache coherency, 5-9, 5-28

cache control instructions, 5-28

registers, 6-30-6-34

structure, 5-6

machine check APU, 5-5

rfmci instruction, 5-12

memory coherency

atomic update memory references, 5-28

memory access ordering, 5-28

memory management unit (MMU), 5-24

address translation, 5-26

registers, 6-34-6-42

MMU assist registers (MAS1–MAS4, MAS6), 5-27

process ID registers (PID0–PID2), 5-27

TLB coherency, 5-27

TLB instructions, 5-26, 5-27

two-level MMU structure, 5-25

memory/cache attributes (WIMGE), 5-29

overview, 1-8, 5-1

performance monitor, 5-29

instructions, 5-12

purposes, 5-5

registers, 6-51-6-54

power management, 5-10

processor control registers, 6-11-6-15

programming model

instruction set, 5-12

registers diagram, 5-18

registers

BBEAR (branch buffer address register), 6-25

BBTAR (branch buffer target address register), 6-25

BUCSR (branch unit control and status register), 6-26

CR (condition register), 6-9

CSRR0 (critical save/restore register 0), 6-18

CSRR1 (critical save/restore register 1), 6-19

CTR (count register), 6-11

DACn (data address compare registers 1–2), 6-48

DBCRn (debug control register 0–2), 6-42-6-46

DBSR (debug status register), 6-46

DEAR (data exception address register 0), 6-19

DEC (decrementer register), 6-17

DECAR (decrementer auto-reload register), 6-17

ESR (exception syndrome register), 6-20

GPRs (general-purpose registers), 6-8

HID0 (hardware implementation-dependent register 0),

6-27

HID1 (hardware implementation-dependent register 1),

6-28

IACn (instruction address compare registers 1–2), 6-47

IVORn (interrupt vector offset registers), 6-19

IVPR (interrupt vector prefix register), 6-19

L1CFG0 (L1 cache configuration register 0), 6-32

L1CFG1 (L1 cache configuration register 1), 6-33

L1CSR0 (L1 cache status and control register 0), 6-30

L1CSR1 (L1 cache status and control register 1), 6-31

LR (link register), 6-11

MAS0–MAS6 (MMU assist registers 0–6), 5-27,

6-37-6-42

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