MPC8540 datasheet(1279/1302 Pages) FREESCALE

1279 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 2-1

Index 2

General Index

Accumulator (ACC), 6-50

Acronyms and abbreviated terms, list, lxxxviii

Address maps

addressing on PCI/PCI-X bus, 16-59

device address map overview, 1-20

Address mask (LBC), 13-13

Address multiplexing (LBC SDRAM), 13-54

Address translation and mapping units (ATMUs)

inbound windows, 2-9

illegal interactions between inbound ATMUs and local

access windows, 2-9

PCI/PCI-X—4 windows, 2-9, 16-24

RapidIO—4 windows plus default, 2-9, 17-40-17-43,

17-107-17-109

local access windows, 2-3-2-9

see also Local access windows

outbound windows, 2-8

PCI/PCI-X—4 windows, 16-20

RapidIO—8 windows plus default, 17-37-17-40,

17-106-17-107

processing across the OCeaN fabric, 1-20

Address translation, see e500 core, memory management unit

(MMU)

Addressing

PCI bus addressing, 16-60

configuration space, 16-60

I/O space, 16-60

memory space, 16-59

Alignment, byte (PCI/PCI-X), 16-61

Application examples, 1-21-1-24

control processing, 1-21

APUs

accumulator, 6-50

Arbitration

I2C interface

arbitration control, 11-14

loss of arbitration—forcing of slave mode, 11-23

procedure for arbitration, 11-14

PCI/PCI-X, 16-5, 16-53

Architecture, overview of device, 1-8

ASLEEP (global utilities asleep) signal, 18-2, 18-24

ATMUs, see Address translation and mapping units

BBEAR (branch buffer address register), see e500 core,

registers

BBTAR (branch buffer target address register), see e500 core,

registers

Block diagrams

DDR controller, 9-1, 9-25

debug modes, watchpoint monitor, and trace buffer, 20-1

DMA controller, 15-1

DUART, 12-2

e500 coherency module (ECM), 8-1

e500 core complex, 5-1

FEC, 21-5

I2C interface, 11-1

interrupt controller (PIC), 10-1, 10-43

L2 cache/SRAM, 7-1

local bus controller (LBC), 13-1

PCI/PCI-X controller, 16-1

performance monitor, 19-2

TSEC, 14-6

Book E architecture, see e500 core, Book E architecture

Boot mode

CPU holdoff (POR), 4-15, 8-4

POR status register (PORBMSR), 18-5

Boot page translation, 4-7

Boot ROM location (POR), 4-14

Boot sequencer

boot holdoff mode (POR), 4-16, 8-4

boot page translation, 4-7

I2C interface, 11-2, 11-17-11-19

overview, 1-16, 4-8

POR configuration, 4-16

BUCSR (branch unit control and status register), see e500

core, registers

Buffer descriptors

see FEC controller, buffer descriptors

see TSEC, buffer descriptors

Burst operations (PCI)

see PCI/PCI-X controller, bus protocol

Bus operations

PCI/PCI-X, see PCI/PCI-X controller, bus protocol

Byte alignment (PCI/PCI-X), 16-61

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