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MPC8540 Datasheet(PDF) 1282 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1282 Page - Freescale Semiconductor, Inc |
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1282 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Index 2-4 Freescale Semiconductor E–E overview, 1-18, 15-1 performance monitor events, 19-18 register descriptions, 15-10-15-28 by acronym, see Register Index signal select—channel 2 and 3, 18-12, 18-29 signals summary, 15-5 see also Signals, DMA controller system considerations, 15-41 unusual scenarios, 15-43 DMA to configuration and control registers, 15-44 DMA to DUART, 15-44 DMA to e500 core, 15-43 DMA to Ethernet, 15-44 DMA to I2C, 15-44 transfer interfaces, 15-37 DMA_DACK[0:3] (DMA acknowledge) signals, 15-6 DMA_DDONE[0:3] (DMA done) signals, 15-6 DMA_DREQ[0:3] (DMA request) signals, 15-6 Doorbell message controller see RapidIO controller, message unit Doze mode, 1-19, 18-23 see also Global utilities, power management DUART asynchronous communication bits, 12-2 parity bit, 12-22 START bit, 12-21 STOP bit, 12-22 baud-rate generator logic, 12-22 block diagram, 12-2 divisor latch access bit (ULCRn[DLAB]), 12-4, 12-12 error handling, 12-23 framing error, 12-9, 12-16, 12-21, 12-22, 12-23 overrun error, 12-23 parity error, 12-23 errors detected, 12-3 features, 12-2 functional description, 12-20 initialization/application information, 12-25 interrupts interrupt control logic, 12-25 interrupt enable and control registers, 12-9-12-11 memory map/register definition, 12-4 modes of operation, 12-3 DMA mode selection, 12-24 FIFO mode, 12-24 interrupts, 12-24 local loop-back mode, 12-22 overview, 1-16, 12-1 PC16450 UART compatibility, 12-2 performance monitor events, 19-27 register descriptions, 12-4, 12-6-12-20 by acronym, see Register Index UART0 register offsets, 12-4 UART1 register offsets, 12-4 serial interface data format, 12-2 serial interface operation, 12-20-12-22 data transfer, 12-21 START bit, 12-21 STOP bit, 12-22 transaction protocol example, 12-21 signals summary, 12-3 see also Signals, DUART E e500 coherency module (ECM) block diagram, 8-1 CCB arbiter, 8-9 CCB interface, 8-10 configuration CCB address configuration register (EEBACR), 8-3 CCB port configuration register (EEBPCR), 8-4 error handling error handling registers, 8-5-8-8 features, 8-2 functional description, 8-9 global data multiplexor, 8-10 I/O arbiter, 8-9 initialization/application information, 8-10-8-11 interrupts ECM error enable register (EEER), 8-6 memory map/register definition, 8-2 overview, 1-14, 8-1 performance monitor events, 19-18 register descriptions, 8-3 by acronym, see Register Index transaction queue, 8-9 e500 core block diagram, 5-1 Book E architecture auxiliary processing units (APUs), 5-3 branch target buffer (BTB) locking, 5-5, 5-13 cache line lock and unlock, 5-5, 5-12 integer select (isel), 5-5 machine check, 5-5, 5-12 performance monitor, 5-5, 5-12, 5-29 single-precision floating-point (SPFP), 5-12 future upward compatibility and SPE APU, 5-3 legacy support of PowerPC architecture, 5-31 exception handling, 5-32 instruction set compatibility, 5-31 little-endian mode, 5-33 memory management unit (MMU) and TLBs, 5-32 reset operation, 5-32 boot mode (POR), 4-15 |
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