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MPC8540 Datasheet(PDF) 1280 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1280 Page - Freescale Semiconductor, Inc |
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1280 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Index 2-2 Freescale Semiconductor C–D C Chaining performance monitor events, 19-27 CKSTP_IN (global utilities checkstop in) signal, 18-3 CKSTP_OUT (global utilities checkstop out) signal, 18-3 CLK_OUT (global utilities clock out) signal, 18-3, 18-18 Clocks clock out (CLK_OUT), see Global utilities DDR clock distribution, 9-27, 9-38 device clock signals summary, 4-3 see also Signals, clock device clocking operation, 4-23-4-26 CCB (platform) clock, 4-23 Ethernet clocks, 4-25 overview, 1-20 RapidIO clocks, 4-24 system clock/PCI clock, 4-23 e500 core clock multipliers, 5-11 see also Clocks, POR settings I 2C clock stretching, 11-17 clock synchronization, 11-16 input synchronization and digital filter, 11-16 LBC bus clocks and clock ratios, 13-4 clock ratio register (LCRR), 13-32 PCI/PCI-X clocking, 16-57, 16-62 POR settings e500 core PLL ratio, 4-13 RapidIO transmit clock source, 4-18 system/CCB PLL ratio, 4-12 TSEC inputs and outputs, 14-11 management clock out (EC_MDC), 14-55 Coherency rules L1 caches, 5-28 L2 cache, 7-22 Commands PCI, see PCI/PCI-X controller Configuration DDR, 9-10-9-17, 9-28 ECM CCB address configuration register (EEBACR), 8-3 CCB port configuration register (EEBPCR), 8-4 LBC configuration register (LBCR), 13-31 SDRAM configurations supported, 13-51 PCI configuration cycles, 16-70 configuration space header, 16-70 host accessing PCI configuration space, 16-72 type 0 configuration translation, 16-74 type 1 configuration translation, 16-76 PCI-X configuration transactions, 16-93 PIC global configuration register, 10-17 POR, see Power-on-reset (POR) RapidIO configuration/error injection registers, 17-34-17-36 TSEC interfaces, 14-131-14-151 Configuration space PCI/PCI-X addressing, 16-60 Configuration, control, and status accessing CCSR memory from external masters, 2-11 accessing CCSRs, 4-4 alternate configuration space (ALTBAR and ALTCAR), 4-5 boot page translation, 4-7 CCSR and RapidIO registers, 2-15 CCSR memory map, 2-10-2-16 CCSRBAR update guidelines, 4-4 memory map/register definition, 4-3 organization of CCSR memory, 2-11 Context ID registers, 20-24-20-25 Conventions notational, lxxxvii Core complex bus (CCB), see e500 core, core complex bus (CCB) CR (condition register), see e500 core, registers Critical interrupts see also Interrupt controller (PIC), critical interrupts see e500 core, critical interrupts CSRR0 (critical save/restore register 0), see e500 core, registers CSRR1 (critical save/restore register 1), see e500 core, registers CTR (count register), see e500 core, registers CTS, see DUART_CTS[0:1] D DACn (data address compare registers 1–2), see e500 core, registers Data cache see also e500 core, L1 caches Data cache, see L2 cache/SRAM Data processing with the e500 coherency module (ECM), 1-21 DBCRn (debug control register 0–2), see e500 core, registers DBSR (debug status register), see e500 core, registers DDR controller address signal mappings, 9-4 block diagram, 9-1, 9-25 clock distribution, 9-38 DLL operation, 9-27 |
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