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MPC8540 Datasheet(PDF) 1285 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1285 Page - Freescale Semiconductor, Inc |
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1285 / 1302 page  G–G MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor Index 2-7 frame transmission, 21-52 initialization sequence, 21-50 hardware controlled initialization, 21-50 user initialization, 21-50 inter-packet gap time, 21-61 interrupt handling, 21-59-21-60 clocks operation, 4-25 error handling, 21-61-21-63 features, 21-6 functional description, 21-48 hash function hash table algorithm, 21-57 hash table effectiveness, 21-57 registers, 21-45 interrupts, 21-59 interrupt registers, 21-13-21-18 MAC functionality, 21-36-21-45 configuration, 21-36 CSMA/CD controlling, 21-36 packet collisions, 21-36 packet flow, 21-37 registers, 21-38 memory map/register definition, 21-9 detailed memory map, 21-10-21-13 top level module map, 21-9 modes of operation, 21-7 10 Mbps and 100 Mbps MII operation, 21-7 address recognition options, 21-7 full and half-duplex operation, 21-7 internal and external loop back, 21-61 overview, 1-16, 21-5 physical interface connections, 21-48 media-independent interface (MII), 21-48 register descriptions, 21-13 by acronym, see Register Index FIFO control and status registers, 21-21-21-25 general control and status registers, 21-13-21-21 hash function registers, 21-45-21-46 MAC registers, 21-36-21-45 receive control and status registers, 21-31-21-36 transmit control and status registers, 21-25-21-31 signals, 21-7-21-9 see also Signals, FEC soft reset and reconfiguring procedure, 21-51 FEC_COL (FEC collision input) signals, 21-8 FEC_CRS (FEC carrier sense input) signals, 21-8 FEC_RX_CLK (FEC receive clock) signals, 21-8 FEC_RX_DV (FEC receive data valid) signals, 21-8 FEC_RX_ER (FEC receive error) signals, 21-8 FEC_RXD[3:0] (FEC receive data in) signals, 21-8 FEC_TX_CLK (FEC transmit clock in) signals, 21-8 FEC_TX_EN (FEC transmit data valid in) signals, 21-8 FEC_TX_ER (FEC transmit error in) signals, 21-9 FEC_TXD[3:0] (FEC transmit data out) signals, 21-8 G General-purpose I/O (PCI and TSEC2) see Global utilities Global utilities clock out CLK_OUT signal, 18-3, 18-18 clock out control register (CLKOCR), 18-18 overview, 18-2 DDR DLL control register (DDRDLLCR), 18-19 DMA signal multiplex control register (PMUXCR), 18-12, 18-29 features, 18-1 functional description, 18-21 general-purpose I/O signals (PCI and TSEC2), 18-1 control register (GPIOCR), 18-10 input data register (GPINDR), 18-12 operation of, 18-29 output data register (GPOUTDR), 18-11 interrupt and local bus signal multiplexing, 18-2, 18-12 operation, 18-29 interrupts and power management, 18-27 LBC DLL control register (LBDLLCR), 18-20 machine check summary sources of mcp (MCPSUMR), 18-16 memory map/register definition, 18-3 overview, 18-1 POR configuration boot mode status register (PORBMSR), 18-5 debug mode status register (PORDBGMSR), 18-9 device status register (PORDEVSR), 18-7 I/O impedance status register (PORIMPSCR), 18-6 LAD[0:31] external system configuration (GPPORCR), 4-23, 18-9 PLL status register (PORPLLSR), 18-4 see also Power-on reset (POR) power management and interrupts, 18-27 and snooping, 18-28 block disable (DEVDISR), 18-13, 18-22 CKSTP_IN and core-stopped mode, 18-22 core and device control bits, 18-24 core and device modes, 18-21 device mode control and status register (POWMGTCSR), 18-15 doze mode, 18-23 dynamic power management, 18-22 features, 18-1 functional description, 18-21 |
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