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MPC8540 Datasheet(PDF) 1287 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 1287 Page - Freescale Semiconductor, Inc |
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1287 / 1302 page  I–I MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor Index 2-9 IACn (instruction address compare registers 1–2), see e500 core, registers Initialization DDR (initialization and application information), 9-49 ECM (initialization and application information), 8-10-8-11 I 2C interface (initialization and application information), 11-20-11-24 boot sequencer mode, see I 2C interface, boot sequencer mode generation of SCL when SDA low, 11-22 initialization sequence, 11-20 post-transfer software response, 11-21 repeated START generation, 11-22 START generation, 11-11, 11-21 STOP generation, 11-12, 11-22 L2 cache/SRAM, 7-34-7-36 LBC (initialization and application information), 13-84-13-121 LBC SDRAM power-on initialization, 13-52 PCI/PCI-X (initialization and application information), 16-99-16-101 PIC (initialization and application information), 10-48 RapidIO (initialization and application information), 17-122 TSEC (initialization and application information), 14-131-14-151 see also TSEC, configuration watchpoint monitor and trace buffer, 20-33 Intel PC133 SDRAM commands (LBC), 13-52 Interrupt controller (PIC) block diagram, 10-1, 10-43 configuration (global), 10-17 critical interrupts, 10-7, 10-27, 10-33 destination (interrupt routing), 10-33 critical interrupt to core, 10-7 external interrupt to core, 10-7 IRQ_OUT, 10-7 see also e500 core, critical interrupts end of interrupt (EOI), 10-42, 10-46 external interrupts routed to critical interrupt (cint), 10-28 routed to IRQ_OUT, 10-26 features, 10-3 flow (interrupt processing), 10-43 functional description, 10-43 global timers, 10-20, 10-47 cascading of timers, 10-24, 10-25 clocking of timers, 10-21, 10-25 RTC (real time clock) signal options, 4-3, 4-25, 10-24, 10-25 initialization/application information, 10-48 interrupt acknowledge (IACK) signaling, 10-41, 10-46 interrupt routing (mixed mode), 10-7, 10-43 interrupt source priorities, 10-45 memory map/register definition, 10-9 messaging interrupts, 10-26, 10-28, 10-47 modes of operation, 10-5, 10-17 mixed mode, 10-5 pass-through mode (to support external interrupt controllers), 10-6 nesting of interrupts, 10-46 overview, 1-15, 10-2 performance monitor events, 19-20 power management (wake up conditions), 10-4 processor core interrupt sources, 10-4 critical interrupt (cint) sources, 10-27 processor current task priority, 10-45 programming guidelines, 10-48 changing interrupt source configuration, 10-50 register descriptions, 10-16 by acronym, see Register Index, 10-16 global registers, 10-16-10-20 global timer registers, 10-20-10-25 interrupt source configuration registers, 10-20-10-23, 10-32-10-37 message registers, 10-30-10-32 non-accessible registers in-service register (ISR), 10-45 interrupt pending register (IPR), 10-43 interrupt request register (IRR), 10-43 per-CPU registers, 10-38-10-42 performance monitor mask registers, 10-28-10-30 summary registers, 10-26-10-28 reset of PIC, 10-17, 10-47 reset processor from software, 10-18, 10-46 signals summary, 10-8 see also Signals, PIC simultaneous interrupts, priorities, 10-45 sources of interrupts, 10-6 internal (to PIC) interrupt destinations, 10-27, 10-28 internal (to PIC) interrupt sources, 10-7 spurious vector generation, 10-19, 10-46 vendor identification, 10-17 Interrupts DDR, 9-22 DMA, 15-10-15-14, 15-16, 15-24, 15-27, 15-37 DUART interrupt control logic, 12-25 interrupt enable and control registers, 12-9-12-11 e500 core registers, 6-18-6-24 ECM interrupt register (ECM error enable register—EEER), 8-6 |
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