MPC8540 datasheet(1273/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 1-3

IACK0 (PIC per-CPU processor interrupt acknowledge

IADDRn (FEC individual address registers 0–7), 21-45

IADDRn (TSEC individual address registers 0–7), 14-88

IEVENT (FEC interrupt event register), 21-13

IEVENT (TSEC interrupt event register), 14-20

IFQDPAR (RapidIO inbound frame queue dequeue pointer

address register), 17-75

IFQEPAR (RapidIO inbound frame queue enqueue pointer

address register), 17-76

IFSTAT (FEC interface status register), 21-43

IFSTAT (TSEC interface status register), 14-58

IIDPRn (PIC internal interrupt destination registers 0–31),

10-35

IIVPRn (PIC internal interrupt vector/priority registers

0–31), 10-34

IMASK (FEC interrupt mask register), 21-16

IMASK (TSEC interrupt mask register), 14-23

IMR (RapidIO inbound mailbox mode register), 17-72

INT_ACK (PCI/X interrupt acknowledge register), 16-20

IPGIFG (FEC inter-packet gap/inter-frame gap register),

21-41

IPGIFG (TSEC inter-packet gap/inter-frame gap register),

14-52

IPIDRn (PIC per-CPU interprocessor interrupt dispatch

registers 0–3), 10-39

IPIVPRn (PIC IPI vector/priority registers 0–3), 10-19

IRQSR0 (PIC IRQ_OUT summary register 0), 10-26

IRQSR1 (PIC IRQ_OUT summary register 1), 10-27

ISR (RapidIO inbound mailbox status register), 17-74

JD (TSEC jitter diagnostics register), 14-101

L2CAPTDATAHI (L2 error capture data high register), 7-15

L2CAPTDATALO (L2 error capture data low register), 7-15

L2CAPTECC (L2 error syndrome register), 7-13, 7-16

L2CEWARn (L2 cache external write address registers 0–3),

7-10

L2CEWCRn (L2 cache external write control registers 0–3),

7-10

L2CTL (L2 control register), 7-7

L2ERRADDR (L2 error address capture register), 7-15, 7-20

L2ERRATTR (L2 error attributes capture register), 7-15,

7-19

L2ERRCTL (L2 error control register), 7-15, 7-20

L2ERRDET (L2 error detect register), 7-15, 7-16

L2ERRDIS (L2 error disable register), 7-15, 7-17

L2ERRINJCTL (L2 error injection mask control register),

7-13, 7-14

L2ERRINJHI (L2 error injection mask high register), 7-13

L2ERRINJLO (L2 error injection mask low register), 7-13,

7-14

L2ERRINTEN (L2 error interrupt enable register), 7-15, 7-18

L2SRBARn (L2 memory-mapped SRAM base address

registers 0–1), 7-11

LAWARn (Local access window 0–7 attributes registers), 2-6

LAWBARn (Local access window 0–7 base address

registers), 2-6

LBCR (LBC configuration register), 13-31

LBDLLCR (LBC DLL control register), 18-20

LCRR (LBC clock ratio register), 13-32

LCSBA1CSR (RapidIO local configuration space base

address 1 command and status register), 17-24

LSDMR (LBC SDRAM mode register), 13-22

LSRT (LBC SDRAM refresh timer), 13-25

LTEAR (LBC transfer error address register), 13-30

LTEATR (LBC transfer error attributes register), 13-29

LTEDR (LBC transfer error disable register), 13-27

LTEIR (LBC transfer error interrupt register), 13-28

LTESR (LBC transfer error status register), 13-26

LURT (UPM refresh timer), 13-24

MACCFG1 (FEC MAC configuration register 1), 21-38

MACCFG1 (TSEC MAC configuration register 1), 14-49

MACCFG2 (FEC MAC configuration register 2), 21-40

MACCFG2 (TSEC MAC configuration register 2), 14-51

MACSTNADDR1 (FEC station address part 1 register),

21-43

MACSTNADDR1 (TSEC station address part 1 register),

14-59

MACSTNADDR2 (FEC station address part 2 register),

21-44

MACSTNADDR2 (TSEC station address part 2 register),

14-60

MAR (UPM address register), 13-18

MAXFRM (FEC maximum frame length register), 21-42

MAXFRM (TSEC maximum frame length register), 14-54

MCPSUMR (machine check summary register), 18-16

MDR (UPM data register), 13-22

MER (PIC message enable register), 10-31

MIDRn (PIC messaging interrupt destination registers 0–3),

10-37

MIIMADD (TSEC MII management address register), 14-56

MIIMCFG (TSEC MII management configuration register),

14-54

MIIMCOM (TSEC MII management command register),

14-55

MIIMCON (TSEC MII management control register), 14-57

MIIMIND (TSEC MII management indicator register), 14-58

MIIMSTAT (TSEC MII management status register), 14-57

MPC8540 Datasheet(PDF) 1273 Page - Freescale Semiconductor, Inc

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