MPC8540 datasheet(1271/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Index 1-1

Index 1

AICAR (RapidIO assembly information capability register),

17-15

AIDCAR (RapidIO assembly identity capability register),

17-14

ALTCAR (alternate configuration attribute address register),

4-6

ALTCBAR (alternate configuration base address register),

4-6

ANA (TSEC AN advertisement register), 14-94

ANLPANP (TSEC AN link partner ability next page

ANLPBPA (TSEC AN link partner base page ability

ANNPT (TSEC AN next page transmit register), 14-98

ATTR (FEC attribute register), 21-46

ATTR (TSEC attribute register), 14-89

ATTRELI (FEC attribute extract length and extract index

ATTRELI (TSEC attribute extract length and extract index

BCRn (DMA 0–3 byte count registers), 15-23

BDIDCSR (RapidIO base device ID command and status

BPTR (boot page translation register), 4-8

BRn (LBC base registers 0–7), 13-11

CAM1 (TSEC carry mask register 1), 14-85

CAM2 (TSEC carry mask register 2), 14-86

CAPTURE_ADDRESS (DDR memory error address capture

CAPTURE_ATTRIBUTES (DDR memory error attributes

capture register), 9-23

CAPTURE_DATA_HI (DDR memory data path read capture

high register), 9-19

CAPTURE_DATA_LO (DDR memory data path read

capture low register), 9-20

CAPTURE_ECC (DDR memory data path read capture ECC

CAR1 (TSEC carry register 1), 14-82

CAR2 (TSEC carry register 2), 14-84

CCIDR (current context ID register), 20-24

CCSRBAR (configuration, control, and status registers base

address register), 4-4-4-5

CFG_ADDR (PCI/X configuration address register), 16-18

CFG_DATA (PCI/X configuration data register), 16-19

CISR0 (PIC critical interrupt summary register 0), 10-27

CISR1 (PIC critical interrupt summary register 1), 10-28

CLKOCR (clock out select register), 18-18

CLNDARn (DMA 0–3 current link descriptor address

registers), 15-14

CLSDARn (DMA 0–3 current list-alternate base descriptor

address registers), 15-24

CR (RapidIO configuration register), 17-34

CR (TSEC control register), 14-92

CRBPTR (FEC current receive buffer descriptor pointer

CRBPTR (TSEC current receive buffer descriptor pointer

CSnBNDS (DDR chip select 0–3 bounds registers), 9-10

CSnCONFIG (DDR chip select 0–3 configuration registers),

9-10

CTBPTR (FEC current transmit buffer descriptor pointer

CTBPTR (TSEC current transmit buffer descriptor pointer

CTCSR (RapidIO component tag command and status

CTPR0 (PIC per-CPU processor current task priority

DARn (DMA 0–3 destination address registers), 15-21

DARn (DMA 0–3 destination address registers for

RapidIO maintenance writes), 15-22

DATA_ERR_INJECT_HI (DDR memory data path error

injection mask high register), 9-17

DATA_ERR_INJECT_LO (DDR memory data path error

injection mask low register), 9-18

DATRn (DMA 0–3 destination attributes registers), 15-19

DDR_SDRAM_CFG (DDR SDRAM control configuration

DDR_SDRAM_INTERVAL (DDR SDRAM interval

configuration register), 9-16

MPC8540 Datasheet(PDF) 1271 Page - Freescale Semiconductor, Inc

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