MPC8540 datasheet(1253/1302 Pages) FREESCALE

1253 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-41

21.5.3.1.2, 21-16

Replace the last sentence in the first paragraph with:

“The interrupt signal can be cleared by clearing the corresponding IEVENT

bit.”

21.5.3.1.3, 21-17

Undocument bitfields TXEDIS, CRL/XDADIS, and XFUNDIS.

21.5.3.1.6, 21-20

Remove all references to bitfield DMACTRL[TOD]. This bit position (29)

is now reserved.

21.5.3.2.1, 21-21

Insert the following section as the first subsection of Section 21.

5.3.2:

21.5.3.2.1 FIFO Pause Control Register (FIFO_PAUSE_CTRL)

FIFO_PAUSE_CTRL, shown in Figure 21-11, is writable by the user to

configure the properties of the FEC FIFO.

Table 21-10 describes the fields of the FIFO_PAUSE_CTRL register.

21.5.3.3.1, 21-24

In Table

21-13, replace the bitfield description of TCTRL[TFC_PAUSE] with

the following:

“Transmit flow control pause frame. Use this bit to transmit a PAUSE

frame. To transmit a flow control pause frame, first set

FIFO_PAUSE_CTRL[TFC_PAUSE_EN]. Next, set MACCFG1[GTS]. If

000000000000

Reset

0000_0000_0000_0000

000000000000

TFC_PAUSE_EN

Reset

0000_0000_0000_0000

Offset

0x2_604C

Figure 21-11FIFO_PAUSE_CTRL Register Definition

Table21-10FIFO_PAUSE_CTRL Field Descriptions

Bits

Name

Description

0–29

—

Reserved.

TFC_PAUSE_EN

TFC_PAUSE enable. This bit enables the ability to transmit a pause control frame by setting

the TCTRL[TFC_PAUSE] bit. This bit is cleared at reset.

0 Pause control frame transmission disabled.

1 Pause control frame transmission enabled.

—

Reserved.

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