MPC8540 datasheet(1248/1302 Pages) FREESCALE

1248 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-36

Freescale Semiconductor

Revision History

Ensure that PCI-X configuration transactions are completed before starting

PCI-X data transactions.

Ensure that all PCI-X outbound data traffic is quiesced before attempting

PCI-X configuration transactions. The programmer must ensure all of the

following:

Non-configuration transactions to PCI-X from the processor core are

quiesced.

The core is not fetching instructions from PCI-X.

DMA transactions to PCI-X are quiesced.

RapidIO bridging transactions to PCI-X are quiesced.”

16.4.3.7, 16-88

Add the following before the first sentence:

“As is the case for PCI configuration accesses, the Bus master bit in the

MPC8540’s PCI bus command register must be set before an outbound

configuration access is attempted.”

16.4.3.8.1, 16-91

Add the following between the first and second paragraphs:

“Note that some errors are enabled by programming two bits—one in the

PCI bus command register and another in the PCI/X error enable register

(ERR_EN). Likewise, some errors are reported in two bits—one in the PCI

bus status register and another in the PCI/X error detect register (ERR_DR).

These bits must be cleared separately; that is, clearing one does not clear the

other. For example, clearing the ERR_DR[Mstr abort error] does not clear

the received master abort bit in the PCI bus status register. In these cases,

both bits must be cleared before further error reporting can occur.”

16.4.3.8.1, 16–93

Add the following after Table 16-64:

“When an outbound PCI-X read transaction has been split and the split

completion transaction indicates a master-abort or a target-abort, the

split-completion error message (SCEM) data field contains information for

setting the received master-abort or received target-abort bit in the PCI bus

status register (bits 13 and 12, respectively). However, for misaligned reads

(that is, reads not aligned on a 64-bit boundary), the error is not reflected in

the PCI Status register. The error is reported in the PCI error detection

inferred from the error data capture register (ERR_DL). Drivers that require

this information can read the ERR_DR register rather than the PCI bus

status register.”

MPC8540 Datasheet(PDF) 1248 Page - Freescale Semiconductor, Inc