MPC8540 datasheet(1246/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-34

Freescale Semiconductor

Revision History

In either agent or agent lock mode, access to the internal PCI/X

configuration header by the processor core is handled as described in

Section 16.4.2.11.2, “Accessing the PCI Configuration Space in Host

Mode,” using device = 0 and bus = 0 in PCI CFG_ADDR to indicate the

internal PCI/X header.

16.4.2.13, 16-75

Delete the second and third sentences in the first paragraph.

16.4.2.13.1, 16-75

Delete the last paragraph.

16.4.2.13.2, 16-76

Add the following between the first and second paragraphs:

“Note that some errors are enabled by programming two bits—one in the

PCI bus command register and another in the PCI/X error enable register

(ERR_EN). Likewise, some errors are reported in two bits—one in the PCI

bus status register and another in the PCI/X error detect register (ERR_DR).

These bits must be cleared separately; that is, clearing one does not clear the

other. For example, clearing the ERR_DR[Mstr abort error] does not clear

the received master abort bit in the PCI bus status register. In these cases,

both bits must be cleared before further error reporting can occur.”

16.4.3.6.4, 16-88

Add the following new section that describes the PCI-X split completion

message:

16.4.3.6.4 Split Completion Messages

For PCI-X split completion transactions that include a split completion error

or split completion message, the transaction has a single DWORD data

phase with the format shown in Figure 16-78.

Figure 16-78. PCI-X Split Completion Message Format

Table 16-62 describes the fields of the PCI-X split completion message.

Message Class

Message Index

Remaining Lower

Address

Remaining Lower Address

(cont.)

Remaining Byte Count

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