MPC8540 datasheet(1234/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-22

Freescale Semiconductor

Revision History

14.5.3.6.12, 14-56

In Table 14-43, replace the last row with the following rows:

14.5.3.6.12, 14-55

In Figure 14-45, correct the reset value for the IFSTAT register to be

0x0000_0000.

14.5.3.7.44, 14-79

Correct the first sentence to read:

"Carry register bits are cleared when written with a one."

14.5.3.7.45, 14-80

Correct the first sentence to read:

"Carry register bits are cleared when written with a one."

14.5.3.7.47, 14-83

In Figure 14-94, change bit 30 to be “Reserved”.

14.5.3.8.1, 14-84

Change the third sentence of the first paragraph to read:

“When the DA field of a receive frame is processed through a 32-bit CRC

generator, the 8 high-order bits (0–7) of the CRC remainder are mapped to

one of the 256 entries.”

14.5.3.8.1, 14-85

In Table 14-93, add the following sentence to the IADDRn field description:

“For instance, the MSB of IADDR0 correlates to entry 0 and the LSB of

IADDR7 correlates to entry 255.”

14.5.3.8.2, 14-85

In Table 14-94, add the following sentence to the GADDRn field

description:

“For instance, the MSB of GADDR0 correlates to entry 0 and the LSB of

GADDR7 correlates to entry 255.”

14.5.3.9.2, 14-87

Replace Figure 14-98 with the following figure to correspond to

Table 14-96:

23–27

—

Reserved

Link Fail

Link Fail. This bit indicates the status of signal detection.

0 The100X module has detected a “signal detect” for longer than 330 mS.

1 The100X module has detected a “signal detect” for less than 330 mS or not at all.

29–31

—

Reserved

15 16 17 18

RESET

0000_0000_0000_0000_0000_0000_0000_0000

Offset

TSEC1:0x2_4BFC; TSEC2:0x2_5BFC

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