MPC8540 datasheet(1230/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-18

Freescale Semiconductor

Revision History

duration specified in the received pause control frame and beginning when

the frame was received. 0Control frame not received

Control frame received”

14.5.3.1.1, 14-20

Replace the last two sentences of the first paragraph with:

“Clearing the IEVENT bit clears the interrupt signal. The bit in the IEVENT

effect.”

14.5.3.1.1, 14-21

In Table 14-4, replace the EBERR field description with:

“Ethernet bus error. This bit indicates that a system bus error for a memory

read ocurred while a DMA transaction was underway. If the EBERR is set

while transmission is in progress, the DMA stops sending data to the Tx

FIFO which eventually causes an underrun error (XFUN) and

TSTAT[THLT] is set. If the EBERR is set while receiving a frame, the DMA

discards the frame and RSTAT[QHLT] is set.

No system bus error occurred.

System bus error occurred.”

14.5.3.1.2, 14-22

Replace the last sentence in the first paragraph with:

“The interrupt signal can be cleared by clearing the corresponding IEVENT

bit.”

14.5.3.1.3, 14-24

Undocument bitfields TXEDIS, CRL/XDADIS, and XFUNDIS.

14.5.3.1.7, 14-27 and 28

Remove bitfield DMACTRL[TOD] from Figure 14-12 and Table 14-10.

This bit position (29) is now reserved.

14.5.3.1.7, 14-28

In Table 14-10, add the following paragraph after the second paragraph of

the WOP field description:

“A buffer descriptor is considered not ready when its TxBD[Ready] field is

clear or its TxBD[Data Length] field is zero. It is considered ready when

both TxBD[Ready] is set and TxBD[Data Length] is non-zero.”

14.5.3.1.7, 14-28

In Table 14-10, change the second sentence of the third paragraph (which

becomes the fourth paragraph after incorporating of the above errata) of the

WOP field description to read:

“If the TxBD becomes ready, TSEC continues to process the frame.”

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