MPC8540 datasheet(1231/1302 Pages) FREESCALE

1231 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-19

14.5.3.2.1, 14-30

Insert the following section as the first subsection of Section 14.5.3.2:

14.5.3.2.1 FIFO Pause Control Register (FIFO_PAUSE_CTRL)

FIFO_PAUSE_CTRL, shown in Figure 14-20, is writable by the user

to configure the properties of the TSEC FIFO.

Table 14-20 describes the fields of the FIFO_PAUSE_CTRL register.

14.5.3.3.1, 14-32

In Table

14-15, replace the bitfield description of TCTRL[TFC_PAUSE] with

the following:

“Transmit flow control pause frame. Use this bit to transmit a PAUSE

frame. To transmit a flow control pause frame, first set

FIFO_PAUSE_CTRL[TFC_PAUSE_EN]. Next, set MACCFG1[GTS]. If

TFC_PAUSE is then set, the MAC stops transmission of data frames after

the current transmission completes. The GTSC interrupt in the IEVENT

transmits a MAC control PAUSE frame with the duration value obtained

from the PTV register. The TXC interrupt occurs after sending the control

Reset

0000_0000_0000_0000

TFC_PAUSE_EN

Reset

0000_0000_0000_0000

Offset

TSEC1:0x2_404C; TSEC2:0x2_504C

Figure 14-14 FIFO_PAUSE_CTRL Register Definition

Table 14-12 FIFO_PAUSE_CTRL Field Descriptions

Bits

Name

Description

0–29

—

Reserved

TFC_PAUSE_EN TFC_PAUSE enable. This bit enables the ability to transmit a pause control frame by

setting the TCTRL[TFC_PAUSE] bit. This bit is cleared at reset.

0 Pause control frame transmission disabled.

1 Pause control frame transmission enabled.

—

Reserved

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