MPC8540 datasheet(1224/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

A-12

Freescale Semiconductor

Revision History

9.5.4–9.5.7, 9-35–9-39

In all burst examples, re-number the data beats in the figures to be D0, D1,

D2, D3, D0, D1, D2, D3.

9.5.4, 9-35

In the last paragraph, change the phrase, “see Figure 9-26 for a single-beat

read operation,” to read “see Figure 9-26 for a back-to-back burst read

operation,”.

9.5.4, 9-36

Change the title of Figure 9-28 to “DDR SDRAM Burst Write

Timing—ACTTORW = 4”.

9.5.6, 9-38

Change the last sentence of this section to read “Figure 9-31 shows the

registered DDR SDRAM DIMM back-to-back burst write timing.”

9.5.7, 9-39

Replace the existing Figure 9-32 with the figure below:

9.5.8, 9-40

In the paragraph preceding Section 9.5.8.1, change the reference to “Two

sets of auto refresh commands...” to read “Three sets of auto refresh

commands...”. Also, change the reference to “...commands are also

staggered in two groups...” to read “... commands are also staggered in three

groups...”

ACTTORW

ROW

COL

SDRAM Clock

MCS

MCAS

MA[13:0]

MWE

MRAS

MDQ[0:63]

MDQS

MDM[0:7]

1/4 Delay

COL

MDQ[0:63]

MDQS

MDM[0:7]

1/2 Delay

8910

D0 D1 D2 D3 D4 D5 D6 D7

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