MPC8540 datasheet(1223/1302 Pages) FREESCALE

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Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-11

generate a machine check interrupt, unless it is disabled (by clearing

HID1[RFXE]). If RFXE is zero and this error occurs,

ERR_DISABLE[MBED] must be zero and MBEE and

DDR_SDRAM_CFG[ECC_EN] must be set to ensure that an interrupt is

generated. For more information, see Section 6.10.2, “Hardware

Implementation-Dependent Register 1 (HID1).”

Multiple-bit ECC errors cannot generate interrupts.

Multiple-bit ECC errors generate interrupts.”

9.5, 9-25

Replace Figure 9-21 with the figure below:

9.5, 9-25

Remove the last sentence of the fourth paragraph.

9.5.1.1, 9-30

In the first two columns of Table 9-26, change “Mbytes” to “Mbits” and

“Gbytes” to “Gbits”.

9.5.1.1, 9-30

Delete the second-to-last paragraph of this sentence that starts with the

words, “If a disabled bank...”

Address

Decode

Request from

Master

Input

Staging

Queue

Physical Bank,

Logical Bank,

Row

Open

Address

Control

DDR SDRAM

Memory Array:

MA[0:14]

MBAA[0:1]

Debug Signals:

MSRCID[0:4]

MDVAL

DDR SDRAM

Memory Control:

MCS[0:3]

MCAS

MRAS

MWE

MDM[0:8]

MCKE[0:1]

Data Strobes:

MDQS[0:8]

Data Signals:

MDQ[0:63]

MECC[0:7]

Address from

Master

SDRAM

Control

Row

Open

Table

Delay Chain

NEG

ECC

Error

Signals

ECC

RMW

ECM

To Error

Management

Data from

SDRAM

Data from

Master

Clocks:

MCK[0:5]

MSYNC_OUT

MSYNC_IN

DLL

FIFO

POS

FIFO

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