MPC8540 datasheet(1219/1302 Pages) FREESCALE

1219 / 1302 page

Changes From Revision 0 to Revision 1

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

A-7

3. Very soon after the cache external write, a transaction to clear the

lock occurs. This can be caused by the processor executing a dcblc or

icblc instruction with CT = 1, or by the ECM mastering a lock clear

transaction.

If this scenario occurs within a tight timing window, the cache line

may unexpectedly remain locked at the end of the sequence.

The interrupt handler may want to clear the erroneously remaining

lock in this case.

7.9, 7-28

Add new Section 7.9.2, “Flash Invalidation of L2 Cache” as follows:

“The L2 cache may be completely invalidated by setting the L2I bit of the

L2 control register (L2CTL). Note that no data is lost in this process because

the L2 cache is a write-through cache and contains no modified data. Flash

invalidation of the cache is necessary when the cache is initially enabled and

may be necessary to recover from some error conditions such as a tag parity

error.

The invalidation process requires several cycles to complete. The L2I bit

remains set during this procedure and is then cleared automatically when

the procedure is complete. The L2 cache controller issues retries for all

transactions on the e500 core complex bus (CCB) while the flash

invalidation process is in progress.

Note that the contents of memory-mapped SRAM regions of the data array

are unaffected by a flash invalidation of the L2 cache regions fo the array.

7.10, 7-32

Add new Section 7.10, “Initialization/Application Information,” with the

following sections: Section 7.10.1, “Initialization,” with new subsections

Section 7.9.1.1, “L2 Cache Initialization,” and Section 7.9.1.2,

“Memory-Mapped SRAM Initialization.”

7.9.1.1 L2 Cache Initialization

After power-on reset, the valid bits in the L2 cache status array are in

random states. Therefore, it is necessary to perform a flash invalidate

operation before using the array as an L2 cache. This is done by writing a 1

to the L2I bit of the L2 control register (L2CTL). This can be done before

or simultaneously with the write that enables the L2 cache. That is, the L2E

and L2I bits of L2CTL can be set simultaneously. The L2I bit clears

automatically, so no further writes are necessary.

MPC8540 Datasheet(PDF) 1219 Page - Freescale Semiconductor, Inc